1*4f6ad66aSAchin Gupta/* 2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved. 3*4f6ad66aSAchin Gupta * 4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 6*4f6ad66aSAchin Gupta * 7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 9*4f6ad66aSAchin Gupta * 10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 13*4f6ad66aSAchin Gupta * 14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 16*4f6ad66aSAchin Gupta * prior written permission. 17*4f6ad66aSAchin Gupta * 18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*4f6ad66aSAchin Gupta */ 30*4f6ad66aSAchin Gupta 31*4f6ad66aSAchin Gupta#include <platform.h> 32*4f6ad66aSAchin Gupta 33*4f6ad66aSAchin GuptaOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34*4f6ad66aSAchin GuptaOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35*4f6ad66aSAchin Gupta 36*4f6ad66aSAchin Gupta 37*4f6ad66aSAchin GuptaMEMORY { 38*4f6ad66aSAchin Gupta /* RAM is read/write and Initialised */ 39*4f6ad66aSAchin Gupta RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE 40*4f6ad66aSAchin Gupta} 41*4f6ad66aSAchin Gupta 42*4f6ad66aSAchin Gupta 43*4f6ad66aSAchin GuptaSECTIONS 44*4f6ad66aSAchin Gupta{ 45*4f6ad66aSAchin Gupta . = BL31_BASE; 46*4f6ad66aSAchin Gupta 47*4f6ad66aSAchin Gupta BL31_RO ALIGN (4096): { 48*4f6ad66aSAchin Gupta *(entry_code) 49*4f6ad66aSAchin Gupta *(.text) 50*4f6ad66aSAchin Gupta *(.rodata) 51*4f6ad66aSAchin Gupta } >RAM 52*4f6ad66aSAchin Gupta 53*4f6ad66aSAchin Gupta BL31_STACKS ALIGN (4096): { 54*4f6ad66aSAchin Gupta . += 0x1000; 55*4f6ad66aSAchin Gupta *(tzfw_normal_stacks) 56*4f6ad66aSAchin Gupta } >RAM 57*4f6ad66aSAchin Gupta 58*4f6ad66aSAchin Gupta BL31_COHERENT_RAM ALIGN (4096): { 59*4f6ad66aSAchin Gupta *(tzfw_coherent_mem) 60*4f6ad66aSAchin Gupta /* . += 0x1000;*/ 61*4f6ad66aSAchin Gupta /* Do we need to ensure at least 4k here? */ 62*4f6ad66aSAchin Gupta . = ALIGN(4096); 63*4f6ad66aSAchin Gupta } >RAM 64*4f6ad66aSAchin Gupta 65*4f6ad66aSAchin Gupta __BL31_DATA_START__ = .; 66*4f6ad66aSAchin Gupta .bss ALIGN (4096): { 67*4f6ad66aSAchin Gupta *(.bss) 68*4f6ad66aSAchin Gupta *(COMMON) 69*4f6ad66aSAchin Gupta } >RAM 70*4f6ad66aSAchin Gupta 71*4f6ad66aSAchin Gupta .data : { 72*4f6ad66aSAchin Gupta *(.data) 73*4f6ad66aSAchin Gupta } >RAM 74*4f6ad66aSAchin Gupta __BL31_DATA_STOP__ = .; 75*4f6ad66aSAchin Gupta 76*4f6ad66aSAchin Gupta 77*4f6ad66aSAchin Gupta __BL31_RO_BASE__ = LOADADDR(BL31_RO); 78*4f6ad66aSAchin Gupta __BL31_RO_SIZE__ = SIZEOF(BL31_RO); 79*4f6ad66aSAchin Gupta 80*4f6ad66aSAchin Gupta __BL31_STACKS_BASE__ = LOADADDR(BL31_STACKS); 81*4f6ad66aSAchin Gupta __BL31_STACKS_SIZE__ = SIZEOF(BL31_STACKS); 82*4f6ad66aSAchin Gupta 83*4f6ad66aSAchin Gupta __BL31_COHERENT_RAM_BASE__ = LOADADDR(BL31_COHERENT_RAM); 84*4f6ad66aSAchin Gupta __BL31_COHERENT_RAM_SIZE__ = SIZEOF(BL31_COHERENT_RAM); 85*4f6ad66aSAchin Gupta 86*4f6ad66aSAchin Gupta __BL31_RW_BASE__ = __BL31_DATA_START__; 87*4f6ad66aSAchin Gupta __BL31_RW_SIZE__ = __BL31_DATA_STOP__ - __BL31_DATA_START__; 88*4f6ad66aSAchin Gupta} 89