1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <common/runtime_svc.h> 14#include <context.h> 15#include <lib/el3_runtime/cpu_data.h> 16#include <lib/smccc.h> 17 18 .globl runtime_exceptions 19 20 .globl sync_exception_sp_el0 21 .globl irq_sp_el0 22 .globl fiq_sp_el0 23 .globl serror_sp_el0 24 25 .globl sync_exception_sp_elx 26 .globl irq_sp_elx 27 .globl fiq_sp_elx 28 .globl serror_sp_elx 29 30 .globl sync_exception_aarch64 31 .globl irq_aarch64 32 .globl fiq_aarch64 33 .globl serror_aarch64 34 35 .globl sync_exception_aarch32 36 .globl irq_aarch32 37 .globl fiq_aarch32 38 .globl serror_aarch32 39 40 /* 41 * Macro that prepares entry to EL3 upon taking an exception. 42 * 43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 44 * instruction. When an error is thus synchronized, the handling is 45 * delegated to platform EA handler. 46 * 47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 48 * Asynchronous External Aborts. 49 */ 50 .macro check_and_unmask_ea 51#if RAS_EXTENSION 52 /* Synchronize pending External Aborts */ 53 esb 54 55 /* Unmask the SError interrupt */ 56 msr daifclr, #DAIF_ABT_BIT 57 58 /* 59 * Explicitly save x30 so as to free up a register and to enable 60 * branching 61 */ 62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 63 64 /* Check for SErrors synchronized by the ESB instruction */ 65 mrs x30, DISR_EL1 66 tbz x30, #DISR_A_BIT, 1f 67 68 /* Save GP registers and restore them afterwards */ 69 bl save_gp_registers 70 bl handle_lower_el_ea_esb 71 bl restore_gp_registers 72 731: 74#else 75 /* Unmask the SError interrupt */ 76 msr daifclr, #DAIF_ABT_BIT 77 78 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 79#endif 80 .endm 81 82 /* --------------------------------------------------------------------- 83 * This macro handles Synchronous exceptions. 84 * Only SMC exceptions are supported. 85 * --------------------------------------------------------------------- 86 */ 87 .macro handle_sync_exception 88#if ENABLE_RUNTIME_INSTRUMENTATION 89 /* 90 * Read the timestamp value and store it in per-cpu data. The value 91 * will be extracted from per-cpu data by the C level SMC handler and 92 * saved to the PMF timestamp region. 93 */ 94 mrs x30, cntpct_el0 95 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 96 mrs x29, tpidr_el3 97 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 98 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 99#endif 100 101 mrs x30, esr_el3 102 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 103 104 /* Handle SMC exceptions separately from other synchronous exceptions */ 105 cmp x30, #EC_AARCH32_SMC 106 b.eq smc_handler32 107 108 cmp x30, #EC_AARCH64_SMC 109 b.eq smc_handler64 110 111 /* Synchronous exceptions other than the above are assumed to be EA */ 112 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 113 b enter_lower_el_sync_ea 114 .endm 115 116 117 /* --------------------------------------------------------------------- 118 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 119 * interrupts. 120 * --------------------------------------------------------------------- 121 */ 122 .macro handle_interrupt_exception label 123 124 bl save_gp_registers 125 126 /* Save ARMv8.3-PAuth registers and load firmware key */ 127#if CTX_INCLUDE_PAUTH_REGS 128 bl pauth_context_save 129#endif 130#if ENABLE_PAUTH 131 bl pauth_load_bl_apiakey 132#endif 133 134 /* Save the EL3 system registers needed to return from this exception */ 135 mrs x0, spsr_el3 136 mrs x1, elr_el3 137 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 138 139 /* Switch to the runtime stack i.e. SP_EL0 */ 140 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 141 mov x20, sp 142 msr spsel, #0 143 mov sp, x2 144 145 /* 146 * Find out whether this is a valid interrupt type. 147 * If the interrupt controller reports a spurious interrupt then return 148 * to where we came from. 149 */ 150 bl plat_ic_get_pending_interrupt_type 151 cmp x0, #INTR_TYPE_INVAL 152 b.eq interrupt_exit_\label 153 154 /* 155 * Get the registered handler for this interrupt type. 156 * A NULL return value could be 'cause of the following conditions: 157 * 158 * a. An interrupt of a type was routed correctly but a handler for its 159 * type was not registered. 160 * 161 * b. An interrupt of a type was not routed correctly so a handler for 162 * its type was not registered. 163 * 164 * c. An interrupt of a type was routed correctly to EL3, but was 165 * deasserted before its pending state could be read. Another 166 * interrupt of a different type pended at the same time and its 167 * type was reported as pending instead. However, a handler for this 168 * type was not registered. 169 * 170 * a. and b. can only happen due to a programming error. The 171 * occurrence of c. could be beyond the control of Trusted Firmware. 172 * It makes sense to return from this exception instead of reporting an 173 * error. 174 */ 175 bl get_interrupt_type_handler 176 cbz x0, interrupt_exit_\label 177 mov x21, x0 178 179 mov x0, #INTR_ID_UNAVAILABLE 180 181 /* Set the current security state in the 'flags' parameter */ 182 mrs x2, scr_el3 183 ubfx x1, x2, #0, #1 184 185 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 186 mov x2, x20 187 188 /* x3 will point to a cookie (not used now) */ 189 mov x3, xzr 190 191 /* Call the interrupt type handler */ 192 blr x21 193 194interrupt_exit_\label: 195 /* Return from exception, possibly in a different security state */ 196 b el3_exit 197 198 .endm 199 200 201vector_base runtime_exceptions 202 203 /* --------------------------------------------------------------------- 204 * Current EL with SP_EL0 : 0x0 - 0x200 205 * --------------------------------------------------------------------- 206 */ 207vector_entry sync_exception_sp_el0 208 /* We don't expect any synchronous exceptions from EL3 */ 209 b report_unhandled_exception 210end_vector_entry sync_exception_sp_el0 211 212vector_entry irq_sp_el0 213 /* 214 * EL3 code is non-reentrant. Any asynchronous exception is a serious 215 * error. Loop infinitely. 216 */ 217 b report_unhandled_interrupt 218end_vector_entry irq_sp_el0 219 220 221vector_entry fiq_sp_el0 222 b report_unhandled_interrupt 223end_vector_entry fiq_sp_el0 224 225 226vector_entry serror_sp_el0 227 no_ret plat_handle_el3_ea 228end_vector_entry serror_sp_el0 229 230 /* --------------------------------------------------------------------- 231 * Current EL with SP_ELx: 0x200 - 0x400 232 * --------------------------------------------------------------------- 233 */ 234vector_entry sync_exception_sp_elx 235 /* 236 * This exception will trigger if anything went wrong during a previous 237 * exception entry or exit or while handling an earlier unexpected 238 * synchronous exception. There is a high probability that SP_EL3 is 239 * corrupted. 240 */ 241 b report_unhandled_exception 242end_vector_entry sync_exception_sp_elx 243 244vector_entry irq_sp_elx 245 b report_unhandled_interrupt 246end_vector_entry irq_sp_elx 247 248vector_entry fiq_sp_elx 249 b report_unhandled_interrupt 250end_vector_entry fiq_sp_elx 251 252vector_entry serror_sp_elx 253 no_ret plat_handle_el3_ea 254end_vector_entry serror_sp_elx 255 256 /* --------------------------------------------------------------------- 257 * Lower EL using AArch64 : 0x400 - 0x600 258 * --------------------------------------------------------------------- 259 */ 260vector_entry sync_exception_aarch64 261 /* 262 * This exception vector will be the entry point for SMCs and traps 263 * that are unhandled at lower ELs most commonly. SP_EL3 should point 264 * to a valid cpu context where the general purpose and system register 265 * state can be saved. 266 */ 267 check_and_unmask_ea 268 handle_sync_exception 269end_vector_entry sync_exception_aarch64 270 271vector_entry irq_aarch64 272 check_and_unmask_ea 273 handle_interrupt_exception irq_aarch64 274end_vector_entry irq_aarch64 275 276vector_entry fiq_aarch64 277 check_and_unmask_ea 278 handle_interrupt_exception fiq_aarch64 279end_vector_entry fiq_aarch64 280 281vector_entry serror_aarch64 282 msr daifclr, #DAIF_ABT_BIT 283 b enter_lower_el_async_ea 284end_vector_entry serror_aarch64 285 286 /* --------------------------------------------------------------------- 287 * Lower EL using AArch32 : 0x600 - 0x800 288 * --------------------------------------------------------------------- 289 */ 290vector_entry sync_exception_aarch32 291 /* 292 * This exception vector will be the entry point for SMCs and traps 293 * that are unhandled at lower ELs most commonly. SP_EL3 should point 294 * to a valid cpu context where the general purpose and system register 295 * state can be saved. 296 */ 297 check_and_unmask_ea 298 handle_sync_exception 299end_vector_entry sync_exception_aarch32 300 301vector_entry irq_aarch32 302 check_and_unmask_ea 303 handle_interrupt_exception irq_aarch32 304end_vector_entry irq_aarch32 305 306vector_entry fiq_aarch32 307 check_and_unmask_ea 308 handle_interrupt_exception fiq_aarch32 309end_vector_entry fiq_aarch32 310 311vector_entry serror_aarch32 312 msr daifclr, #DAIF_ABT_BIT 313 b enter_lower_el_async_ea 314end_vector_entry serror_aarch32 315 316 /* --------------------------------------------------------------------- 317 * The following code handles secure monitor calls. 318 * Depending upon the execution state from where the SMC has been 319 * invoked, it frees some general purpose registers to perform the 320 * remaining tasks. They involve finding the runtime service handler 321 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 322 * before calling the handler. 323 * 324 * Note that x30 has been explicitly saved and can be used here 325 * --------------------------------------------------------------------- 326 */ 327func smc_handler 328smc_handler32: 329 /* Check whether aarch32 issued an SMC64 */ 330 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 331 332smc_handler64: 333 /* NOTE: The code below must preserve x0-x4 */ 334 335 /* Save general purpose registers */ 336 bl save_gp_registers 337 338 /* Save ARMv8.3-PAuth registers and load firmware key */ 339#if CTX_INCLUDE_PAUTH_REGS 340 bl pauth_context_save 341#endif 342#if ENABLE_PAUTH 343 bl pauth_load_bl_apiakey 344#endif 345 346 /* 347 * Populate the parameters for the SMC handler. 348 * We already have x0-x4 in place. x5 will point to a cookie (not used 349 * now). x6 will point to the context structure (SP_EL3) and x7 will 350 * contain flags we need to pass to the handler. 351 */ 352 mov x5, xzr 353 mov x6, sp 354 355 /* Get the unique owning entity number */ 356 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 357 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 358 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 359 360 /* Load descriptor index from array of indices */ 361 adr x14, rt_svc_descs_indices 362 ldrb w15, [x14, x16] 363 364 /* Any index greater than 127 is invalid. Check bit 7. */ 365 tbnz w15, 7, smc_unknown 366 367 /* 368 * Get the descriptor using the index 369 * x11 = (base + off), w15 = index 370 * 371 * handler = (base + off) + (index << log2(size)) 372 */ 373 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 374 lsl w10, w15, #RT_SVC_SIZE_LOG2 375 ldr x15, [x11, w10, uxtw] 376 377 /* 378 * Restore the saved C runtime stack value which will become the new 379 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 380 * structure prior to the last ERET from EL3. 381 */ 382 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 383 384 /* Switch to SP_EL0 */ 385 msr spsel, #0 386 387 /* 388 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 389 * switch during SMC handling. 390 * TODO: Revisit if all system registers can be saved later. 391 */ 392 mrs x16, spsr_el3 393 mrs x17, elr_el3 394 mrs x18, scr_el3 395 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 396 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 397 398 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 399 bfi x7, x18, #0, #1 400 401 mov sp, x12 402 403 /* 404 * Call the Secure Monitor Call handler and then drop directly into 405 * el3_exit() which will program any remaining architectural state 406 * prior to issuing the ERET to the desired lower EL. 407 */ 408#if DEBUG 409 cbz x15, rt_svc_fw_critical_error 410#endif 411 blr x15 412 413 b el3_exit 414 415smc_unknown: 416 /* 417 * Unknown SMC call. Populate return value with SMC_UNK, restore 418 * GP registers, and return to caller. 419 */ 420 mov x0, #SMC_UNK 421 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 422#if CTX_INCLUDE_PAUTH_REGS 423 bl pauth_context_restore 424#endif 425 b restore_gp_registers_eret 426 427smc_prohibited: 428 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 429 mov x0, #SMC_UNK 430 eret 431 432rt_svc_fw_critical_error: 433 /* Switch to SP_ELx */ 434 msr spsel, #1 435 no_ret report_unhandled_exception 436endfunc smc_handler 437