1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <common/runtime_svc.h> 14#include <context.h> 15#include <lib/el3_runtime/cpu_data.h> 16#include <lib/smccc.h> 17 18 .globl runtime_exceptions 19 20 .globl sync_exception_sp_el0 21 .globl irq_sp_el0 22 .globl fiq_sp_el0 23 .globl serror_sp_el0 24 25 .globl sync_exception_sp_elx 26 .globl irq_sp_elx 27 .globl fiq_sp_elx 28 .globl serror_sp_elx 29 30 .globl sync_exception_aarch64 31 .globl irq_aarch64 32 .globl fiq_aarch64 33 .globl serror_aarch64 34 35 .globl sync_exception_aarch32 36 .globl irq_aarch32 37 .globl fiq_aarch32 38 .globl serror_aarch32 39 40 /* 41 * Macro that prepares entry to EL3 upon taking an exception. 42 * 43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 44 * instruction. When an error is thus synchronized, the handling is 45 * delegated to platform EA handler. 46 * 47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 48 * Asynchronous External Aborts. 49 */ 50 .macro check_and_unmask_ea 51#if RAS_EXTENSION 52 /* Synchronize pending External Aborts */ 53 esb 54 55 /* Unmask the SError interrupt */ 56 msr daifclr, #DAIF_ABT_BIT 57 58 /* 59 * Explicitly save x30 so as to free up a register and to enable 60 * branching 61 */ 62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 63 64 /* Check for SErrors synchronized by the ESB instruction */ 65 mrs x30, DISR_EL1 66 tbz x30, #DISR_A_BIT, 1f 67 68 /* Save GP registers and restore them afterwards */ 69 bl save_gp_registers 70 71 /* 72 * If Secure Cycle Counter is not disabled in MDCR_EL3 73 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and 74 * disable all event counters and cycle counter. 75 */ 76 bl save_pmcr_disable_pmu 77 78 bl handle_lower_el_ea_esb 79 bl restore_gp_registers 80 811: 82#else 83 /* Unmask the SError interrupt */ 84 msr daifclr, #DAIF_ABT_BIT 85 86 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 87#endif 88 .endm 89 90 /* --------------------------------------------------------------------- 91 * This macro handles Synchronous exceptions. 92 * Only SMC exceptions are supported. 93 * --------------------------------------------------------------------- 94 */ 95 .macro handle_sync_exception 96#if ENABLE_RUNTIME_INSTRUMENTATION 97 /* 98 * Read the timestamp value and store it in per-cpu data. The value 99 * will be extracted from per-cpu data by the C level SMC handler and 100 * saved to the PMF timestamp region. 101 */ 102 mrs x30, cntpct_el0 103 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 104 mrs x29, tpidr_el3 105 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 106 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 107#endif 108 109 mrs x30, esr_el3 110 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 111 112 /* Handle SMC exceptions separately from other synchronous exceptions */ 113 cmp x30, #EC_AARCH32_SMC 114 b.eq smc_handler32 115 116 cmp x30, #EC_AARCH64_SMC 117 b.eq smc_handler64 118 119 /* Synchronous exceptions other than the above are assumed to be EA */ 120 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 121 b enter_lower_el_sync_ea 122 .endm 123 124 125 /* --------------------------------------------------------------------- 126 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 127 * interrupts. 128 * --------------------------------------------------------------------- 129 */ 130 .macro handle_interrupt_exception label 131 132 bl save_gp_registers 133 134 /* 135 * If Secure Cycle Counter is not disabled in MDCR_EL3 136 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and 137 * disable all event counters and cycle counter. 138 */ 139 bl save_pmcr_disable_pmu 140 141 /* Save ARMv8.3-PAuth registers and load firmware key */ 142#if CTX_INCLUDE_PAUTH_REGS 143 bl pauth_context_save 144#endif 145#if ENABLE_PAUTH 146 bl pauth_load_bl_apiakey 147#endif 148 149 /* Save the EL3 system registers needed to return from this exception */ 150 mrs x0, spsr_el3 151 mrs x1, elr_el3 152 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 153 154 /* Switch to the runtime stack i.e. SP_EL0 */ 155 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 156 mov x20, sp 157 msr spsel, #0 158 mov sp, x2 159 160 /* 161 * Find out whether this is a valid interrupt type. 162 * If the interrupt controller reports a spurious interrupt then return 163 * to where we came from. 164 */ 165 bl plat_ic_get_pending_interrupt_type 166 cmp x0, #INTR_TYPE_INVAL 167 b.eq interrupt_exit_\label 168 169 /* 170 * Get the registered handler for this interrupt type. 171 * A NULL return value could be 'cause of the following conditions: 172 * 173 * a. An interrupt of a type was routed correctly but a handler for its 174 * type was not registered. 175 * 176 * b. An interrupt of a type was not routed correctly so a handler for 177 * its type was not registered. 178 * 179 * c. An interrupt of a type was routed correctly to EL3, but was 180 * deasserted before its pending state could be read. Another 181 * interrupt of a different type pended at the same time and its 182 * type was reported as pending instead. However, a handler for this 183 * type was not registered. 184 * 185 * a. and b. can only happen due to a programming error. The 186 * occurrence of c. could be beyond the control of Trusted Firmware. 187 * It makes sense to return from this exception instead of reporting an 188 * error. 189 */ 190 bl get_interrupt_type_handler 191 cbz x0, interrupt_exit_\label 192 mov x21, x0 193 194 mov x0, #INTR_ID_UNAVAILABLE 195 196 /* Set the current security state in the 'flags' parameter */ 197 mrs x2, scr_el3 198 ubfx x1, x2, #0, #1 199 200 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 201 mov x2, x20 202 203 /* x3 will point to a cookie (not used now) */ 204 mov x3, xzr 205 206 /* Call the interrupt type handler */ 207 blr x21 208 209interrupt_exit_\label: 210 /* Return from exception, possibly in a different security state */ 211 b el3_exit 212 213 .endm 214 215 216vector_base runtime_exceptions 217 218 /* --------------------------------------------------------------------- 219 * Current EL with SP_EL0 : 0x0 - 0x200 220 * --------------------------------------------------------------------- 221 */ 222vector_entry sync_exception_sp_el0 223#ifdef MONITOR_TRAPS 224 stp x29, x30, [sp, #-16]! 225 226 mrs x30, esr_el3 227 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 228 229 /* Check for BRK */ 230 cmp x30, #EC_BRK 231 b.eq brk_handler 232 233 ldp x29, x30, [sp], #16 234#endif /* MONITOR_TRAPS */ 235 236 /* We don't expect any synchronous exceptions from EL3 */ 237 b report_unhandled_exception 238end_vector_entry sync_exception_sp_el0 239 240vector_entry irq_sp_el0 241 /* 242 * EL3 code is non-reentrant. Any asynchronous exception is a serious 243 * error. Loop infinitely. 244 */ 245 b report_unhandled_interrupt 246end_vector_entry irq_sp_el0 247 248 249vector_entry fiq_sp_el0 250 b report_unhandled_interrupt 251end_vector_entry fiq_sp_el0 252 253 254vector_entry serror_sp_el0 255 no_ret plat_handle_el3_ea 256end_vector_entry serror_sp_el0 257 258 /* --------------------------------------------------------------------- 259 * Current EL with SP_ELx: 0x200 - 0x400 260 * --------------------------------------------------------------------- 261 */ 262vector_entry sync_exception_sp_elx 263 /* 264 * This exception will trigger if anything went wrong during a previous 265 * exception entry or exit or while handling an earlier unexpected 266 * synchronous exception. There is a high probability that SP_EL3 is 267 * corrupted. 268 */ 269 b report_unhandled_exception 270end_vector_entry sync_exception_sp_elx 271 272vector_entry irq_sp_elx 273 b report_unhandled_interrupt 274end_vector_entry irq_sp_elx 275 276vector_entry fiq_sp_elx 277 b report_unhandled_interrupt 278end_vector_entry fiq_sp_elx 279 280vector_entry serror_sp_elx 281 no_ret plat_handle_el3_ea 282end_vector_entry serror_sp_elx 283 284 /* --------------------------------------------------------------------- 285 * Lower EL using AArch64 : 0x400 - 0x600 286 * --------------------------------------------------------------------- 287 */ 288vector_entry sync_exception_aarch64 289 /* 290 * This exception vector will be the entry point for SMCs and traps 291 * that are unhandled at lower ELs most commonly. SP_EL3 should point 292 * to a valid cpu context where the general purpose and system register 293 * state can be saved. 294 */ 295 check_and_unmask_ea 296 handle_sync_exception 297end_vector_entry sync_exception_aarch64 298 299vector_entry irq_aarch64 300 check_and_unmask_ea 301 handle_interrupt_exception irq_aarch64 302end_vector_entry irq_aarch64 303 304vector_entry fiq_aarch64 305 check_and_unmask_ea 306 handle_interrupt_exception fiq_aarch64 307end_vector_entry fiq_aarch64 308 309vector_entry serror_aarch64 310 msr daifclr, #DAIF_ABT_BIT 311 b enter_lower_el_async_ea 312end_vector_entry serror_aarch64 313 314 /* --------------------------------------------------------------------- 315 * Lower EL using AArch32 : 0x600 - 0x800 316 * --------------------------------------------------------------------- 317 */ 318vector_entry sync_exception_aarch32 319 /* 320 * This exception vector will be the entry point for SMCs and traps 321 * that are unhandled at lower ELs most commonly. SP_EL3 should point 322 * to a valid cpu context where the general purpose and system register 323 * state can be saved. 324 */ 325 check_and_unmask_ea 326 handle_sync_exception 327end_vector_entry sync_exception_aarch32 328 329vector_entry irq_aarch32 330 check_and_unmask_ea 331 handle_interrupt_exception irq_aarch32 332end_vector_entry irq_aarch32 333 334vector_entry fiq_aarch32 335 check_and_unmask_ea 336 handle_interrupt_exception fiq_aarch32 337end_vector_entry fiq_aarch32 338 339vector_entry serror_aarch32 340 msr daifclr, #DAIF_ABT_BIT 341 b enter_lower_el_async_ea 342end_vector_entry serror_aarch32 343 344#ifdef MONITOR_TRAPS 345 .section .rodata.brk_string, "aS" 346brk_location: 347 .asciz "Error at instruction 0x" 348brk_message: 349 .asciz "Unexpected BRK instruction with value 0x" 350#endif /* MONITOR_TRAPS */ 351 352 /* --------------------------------------------------------------------- 353 * The following code handles secure monitor calls. 354 * Depending upon the execution state from where the SMC has been 355 * invoked, it frees some general purpose registers to perform the 356 * remaining tasks. They involve finding the runtime service handler 357 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 358 * before calling the handler. 359 * 360 * Note that x30 has been explicitly saved and can be used here 361 * --------------------------------------------------------------------- 362 */ 363func smc_handler 364smc_handler32: 365 /* Check whether aarch32 issued an SMC64 */ 366 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 367 368smc_handler64: 369 /* NOTE: The code below must preserve x0-x4 */ 370 371 /* Save general purpose registers */ 372 bl save_gp_registers 373 374 /* 375 * If Secure Cycle Counter is not disabled in MDCR_EL3 376 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and 377 * disable all event counters and cycle counter. 378 */ 379 bl save_pmcr_disable_pmu 380 381 /* Save ARMv8.3-PAuth registers and load firmware key */ 382#if CTX_INCLUDE_PAUTH_REGS 383 bl pauth_context_save 384#endif 385#if ENABLE_PAUTH 386 bl pauth_load_bl_apiakey 387#endif 388 389 /* 390 * Populate the parameters for the SMC handler. 391 * We already have x0-x4 in place. x5 will point to a cookie (not used 392 * now). x6 will point to the context structure (SP_EL3) and x7 will 393 * contain flags we need to pass to the handler. 394 */ 395 mov x5, xzr 396 mov x6, sp 397 398 /* 399 * Restore the saved C runtime stack value which will become the new 400 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 401 * structure prior to the last ERET from EL3. 402 */ 403 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 404 405 /* Switch to SP_EL0 */ 406 msr spsel, #0 407 408 /* 409 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 410 * switch during SMC handling. 411 * TODO: Revisit if all system registers can be saved later. 412 */ 413 mrs x16, spsr_el3 414 mrs x17, elr_el3 415 mrs x18, scr_el3 416 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 417 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 418 419 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 420 bfi x7, x18, #0, #1 421 422 mov sp, x12 423 424 /* Get the unique owning entity number */ 425 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 426 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 427 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 428 429 /* Load descriptor index from array of indices */ 430 adr x14, rt_svc_descs_indices 431 ldrb w15, [x14, x16] 432 433 /* Any index greater than 127 is invalid. Check bit 7. */ 434 tbnz w15, 7, smc_unknown 435 436 /* 437 * Get the descriptor using the index 438 * x11 = (base + off), w15 = index 439 * 440 * handler = (base + off) + (index << log2(size)) 441 */ 442 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 443 lsl w10, w15, #RT_SVC_SIZE_LOG2 444 ldr x15, [x11, w10, uxtw] 445 446 /* 447 * Call the Secure Monitor Call handler and then drop directly into 448 * el3_exit() which will program any remaining architectural state 449 * prior to issuing the ERET to the desired lower EL. 450 */ 451#if DEBUG 452 cbz x15, rt_svc_fw_critical_error 453#endif 454 blr x15 455 456 b el3_exit 457 458smc_unknown: 459 /* 460 * Unknown SMC call. Populate return value with SMC_UNK and call 461 * el3_exit() which will restore the remaining architectural state 462 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 463 * to the desired lower EL. 464 */ 465 mov x0, #SMC_UNK 466 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 467 b el3_exit 468 469smc_prohibited: 470 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 471 mov x0, #SMC_UNK 472 eret 473 474rt_svc_fw_critical_error: 475 /* Switch to SP_ELx */ 476 msr spsel, #1 477 no_ret report_unhandled_exception 478endfunc smc_handler 479 480 /* --------------------------------------------------------------------- 481 * The following code handles exceptions caused by BRK instructions. 482 * Following a BRK instruction, the only real valid cause of action is 483 * to print some information and panic, as the code that caused it is 484 * likely in an inconsistent internal state. 485 * 486 * This is initially intended to be used in conjunction with 487 * __builtin_trap. 488 * --------------------------------------------------------------------- 489 */ 490#ifdef MONITOR_TRAPS 491func brk_handler 492 /* Extract the ISS */ 493 mrs x10, esr_el3 494 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 495 496 /* Ensure the console is initialized */ 497 bl plat_crash_console_init 498 499 adr x4, brk_location 500 bl asm_print_str 501 mrs x4, elr_el3 502 bl asm_print_hex 503 bl asm_print_newline 504 505 adr x4, brk_message 506 bl asm_print_str 507 mov x4, x10 508 mov x5, #28 509 bl asm_print_hex_bits 510 bl asm_print_newline 511 512 no_ret plat_panic_handler 513endfunc brk_handler 514#endif /* MONITOR_TRAPS */ 515