1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <common/runtime_svc.h> 14#include <context.h> 15#include <lib/el3_runtime/cpu_data.h> 16#include <lib/smccc.h> 17 18 .globl runtime_exceptions 19 20 .globl sync_exception_sp_el0 21 .globl irq_sp_el0 22 .globl fiq_sp_el0 23 .globl serror_sp_el0 24 25 .globl sync_exception_sp_elx 26 .globl irq_sp_elx 27 .globl fiq_sp_elx 28 .globl serror_sp_elx 29 30 .globl sync_exception_aarch64 31 .globl irq_aarch64 32 .globl fiq_aarch64 33 .globl serror_aarch64 34 35 .globl sync_exception_aarch32 36 .globl irq_aarch32 37 .globl fiq_aarch32 38 .globl serror_aarch32 39 40 /* 41 * Macro that prepares entry to EL3 upon taking an exception. 42 * 43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 44 * instruction. When an error is thus synchronized, the handling is 45 * delegated to platform EA handler. 46 * 47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 48 * Asynchronous External Aborts. 49 */ 50 .macro check_and_unmask_ea 51#if RAS_EXTENSION 52 /* Synchronize pending External Aborts */ 53 esb 54 55 /* Unmask the SError interrupt */ 56 msr daifclr, #DAIF_ABT_BIT 57 58 /* 59 * Explicitly save x30 so as to free up a register and to enable 60 * branching 61 */ 62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 63 64 /* Check for SErrors synchronized by the ESB instruction */ 65 mrs x30, DISR_EL1 66 tbz x30, #DISR_A_BIT, 1f 67 68 /* Save GP registers and restore them afterwards */ 69 bl save_gp_registers 70 bl handle_lower_el_ea_esb 71 bl restore_gp_registers 72 731: 74#else 75 /* Unmask the SError interrupt */ 76 msr daifclr, #DAIF_ABT_BIT 77 78 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 79#endif 80 .endm 81 82 /* --------------------------------------------------------------------- 83 * This macro handles Synchronous exceptions. 84 * Only SMC exceptions are supported. 85 * --------------------------------------------------------------------- 86 */ 87 .macro handle_sync_exception 88#if ENABLE_RUNTIME_INSTRUMENTATION 89 /* 90 * Read the timestamp value and store it in per-cpu data. The value 91 * will be extracted from per-cpu data by the C level SMC handler and 92 * saved to the PMF timestamp region. 93 */ 94 mrs x30, cntpct_el0 95 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 96 mrs x29, tpidr_el3 97 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 98 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 99#endif 100 101 mrs x30, esr_el3 102 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 103 104 /* Handle SMC exceptions separately from other synchronous exceptions */ 105 cmp x30, #EC_AARCH32_SMC 106 b.eq smc_handler32 107 108 cmp x30, #EC_AARCH64_SMC 109 b.eq smc_handler64 110 111 /* Synchronous exceptions other than the above are assumed to be EA */ 112 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 113 b enter_lower_el_sync_ea 114 .endm 115 116 117 /* --------------------------------------------------------------------- 118 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 119 * interrupts. 120 * --------------------------------------------------------------------- 121 */ 122 .macro handle_interrupt_exception label 123 bl save_gp_registers 124 /* Save the EL3 system registers needed to return from this exception */ 125 mrs x0, spsr_el3 126 mrs x1, elr_el3 127 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 128 129 /* Switch to the runtime stack i.e. SP_EL0 */ 130 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 131 mov x20, sp 132 msr spsel, #0 133 mov sp, x2 134 135 /* 136 * Find out whether this is a valid interrupt type. 137 * If the interrupt controller reports a spurious interrupt then return 138 * to where we came from. 139 */ 140 bl plat_ic_get_pending_interrupt_type 141 cmp x0, #INTR_TYPE_INVAL 142 b.eq interrupt_exit_\label 143 144 /* 145 * Get the registered handler for this interrupt type. 146 * A NULL return value could be 'cause of the following conditions: 147 * 148 * a. An interrupt of a type was routed correctly but a handler for its 149 * type was not registered. 150 * 151 * b. An interrupt of a type was not routed correctly so a handler for 152 * its type was not registered. 153 * 154 * c. An interrupt of a type was routed correctly to EL3, but was 155 * deasserted before its pending state could be read. Another 156 * interrupt of a different type pended at the same time and its 157 * type was reported as pending instead. However, a handler for this 158 * type was not registered. 159 * 160 * a. and b. can only happen due to a programming error. The 161 * occurrence of c. could be beyond the control of Trusted Firmware. 162 * It makes sense to return from this exception instead of reporting an 163 * error. 164 */ 165 bl get_interrupt_type_handler 166 cbz x0, interrupt_exit_\label 167 mov x21, x0 168 169 mov x0, #INTR_ID_UNAVAILABLE 170 171 /* Set the current security state in the 'flags' parameter */ 172 mrs x2, scr_el3 173 ubfx x1, x2, #0, #1 174 175 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 176 mov x2, x20 177 178 /* x3 will point to a cookie (not used now) */ 179 mov x3, xzr 180 181 /* Call the interrupt type handler */ 182 blr x21 183 184interrupt_exit_\label: 185 /* Return from exception, possibly in a different security state */ 186 b el3_exit 187 188 .endm 189 190 191vector_base runtime_exceptions 192 193 /* --------------------------------------------------------------------- 194 * Current EL with SP_EL0 : 0x0 - 0x200 195 * --------------------------------------------------------------------- 196 */ 197vector_entry sync_exception_sp_el0 198 /* We don't expect any synchronous exceptions from EL3 */ 199 b report_unhandled_exception 200end_vector_entry sync_exception_sp_el0 201 202vector_entry irq_sp_el0 203 /* 204 * EL3 code is non-reentrant. Any asynchronous exception is a serious 205 * error. Loop infinitely. 206 */ 207 b report_unhandled_interrupt 208end_vector_entry irq_sp_el0 209 210 211vector_entry fiq_sp_el0 212 b report_unhandled_interrupt 213end_vector_entry fiq_sp_el0 214 215 216vector_entry serror_sp_el0 217 no_ret plat_handle_el3_ea 218end_vector_entry serror_sp_el0 219 220 /* --------------------------------------------------------------------- 221 * Current EL with SP_ELx: 0x200 - 0x400 222 * --------------------------------------------------------------------- 223 */ 224vector_entry sync_exception_sp_elx 225 /* 226 * This exception will trigger if anything went wrong during a previous 227 * exception entry or exit or while handling an earlier unexpected 228 * synchronous exception. There is a high probability that SP_EL3 is 229 * corrupted. 230 */ 231 b report_unhandled_exception 232end_vector_entry sync_exception_sp_elx 233 234vector_entry irq_sp_elx 235 b report_unhandled_interrupt 236end_vector_entry irq_sp_elx 237 238vector_entry fiq_sp_elx 239 b report_unhandled_interrupt 240end_vector_entry fiq_sp_elx 241 242vector_entry serror_sp_elx 243 no_ret plat_handle_el3_ea 244end_vector_entry serror_sp_elx 245 246 /* --------------------------------------------------------------------- 247 * Lower EL using AArch64 : 0x400 - 0x600 248 * --------------------------------------------------------------------- 249 */ 250vector_entry sync_exception_aarch64 251 /* 252 * This exception vector will be the entry point for SMCs and traps 253 * that are unhandled at lower ELs most commonly. SP_EL3 should point 254 * to a valid cpu context where the general purpose and system register 255 * state can be saved. 256 */ 257 check_and_unmask_ea 258 handle_sync_exception 259end_vector_entry sync_exception_aarch64 260 261vector_entry irq_aarch64 262 check_and_unmask_ea 263 handle_interrupt_exception irq_aarch64 264end_vector_entry irq_aarch64 265 266vector_entry fiq_aarch64 267 check_and_unmask_ea 268 handle_interrupt_exception fiq_aarch64 269end_vector_entry fiq_aarch64 270 271vector_entry serror_aarch64 272 msr daifclr, #DAIF_ABT_BIT 273 b enter_lower_el_async_ea 274end_vector_entry serror_aarch64 275 276 /* --------------------------------------------------------------------- 277 * Lower EL using AArch32 : 0x600 - 0x800 278 * --------------------------------------------------------------------- 279 */ 280vector_entry sync_exception_aarch32 281 /* 282 * This exception vector will be the entry point for SMCs and traps 283 * that are unhandled at lower ELs most commonly. SP_EL3 should point 284 * to a valid cpu context where the general purpose and system register 285 * state can be saved. 286 */ 287 check_and_unmask_ea 288 handle_sync_exception 289end_vector_entry sync_exception_aarch32 290 291vector_entry irq_aarch32 292 check_and_unmask_ea 293 handle_interrupt_exception irq_aarch32 294end_vector_entry irq_aarch32 295 296vector_entry fiq_aarch32 297 check_and_unmask_ea 298 handle_interrupt_exception fiq_aarch32 299end_vector_entry fiq_aarch32 300 301vector_entry serror_aarch32 302 msr daifclr, #DAIF_ABT_BIT 303 b enter_lower_el_async_ea 304end_vector_entry serror_aarch32 305 306 307 /* --------------------------------------------------------------------- 308 * This macro takes an argument in x16 that is the index in the 309 * 'rt_svc_descs_indices' array, checks that the value in the array is 310 * valid, and loads in x15 the pointer to the handler of that service. 311 * --------------------------------------------------------------------- 312 */ 313 .macro load_rt_svc_desc_pointer 314 /* Load descriptor index from array of indices */ 315 adr x14, rt_svc_descs_indices 316 ldrb w15, [x14, x16] 317 318#if SMCCC_MAJOR_VERSION == 1 319 /* Any index greater than 127 is invalid. Check bit 7. */ 320 tbnz w15, 7, smc_unknown 321#elif SMCCC_MAJOR_VERSION == 2 322 /* Verify that the top 3 bits of the loaded index are 0 (w15 <= 31) */ 323 cmp w15, #31 324 b.hi smc_unknown 325#endif /* SMCCC_MAJOR_VERSION */ 326 327 /* 328 * Get the descriptor using the index 329 * x11 = (base + off), w15 = index 330 * 331 * handler = (base + off) + (index << log2(size)) 332 */ 333 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 334 lsl w10, w15, #RT_SVC_SIZE_LOG2 335 ldr x15, [x11, w10, uxtw] 336 .endm 337 338 /* --------------------------------------------------------------------- 339 * The following code handles secure monitor calls. 340 * Depending upon the execution state from where the SMC has been 341 * invoked, it frees some general purpose registers to perform the 342 * remaining tasks. They involve finding the runtime service handler 343 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 344 * before calling the handler. 345 * 346 * Note that x30 has been explicitly saved and can be used here 347 * --------------------------------------------------------------------- 348 */ 349func smc_handler 350smc_handler32: 351 /* Check whether aarch32 issued an SMC64 */ 352 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 353 354smc_handler64: 355 /* 356 * Populate the parameters for the SMC handler. 357 * We already have x0-x4 in place. x5 will point to a cookie (not used 358 * now). x6 will point to the context structure (SP_EL3) and x7 will 359 * contain flags we need to pass to the handler. 360 */ 361 bl save_gp_registers 362 363 mov x5, xzr 364 mov x6, sp 365 366#if SMCCC_MAJOR_VERSION == 1 367 368 /* Get the unique owning entity number */ 369 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 370 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 371 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 372 373 load_rt_svc_desc_pointer 374 375#elif SMCCC_MAJOR_VERSION == 2 376 377 /* Bit 31 must be set */ 378 tbz x0, #FUNCID_TYPE_SHIFT, smc_unknown 379 380 /* 381 * Check MSB of namespace to decide between compatibility/vendor and 382 * SPCI/SPRT 383 */ 384 tbz x0, #(FUNCID_NAMESPACE_SHIFT + 1), compat_or_vendor 385 386 /* Namespace is b'10 (SPRT) or b'11 (SPCI) */ 387#if ENABLE_SPM 388 tst x0, #(1 << FUNCID_NAMESPACE_SHIFT) 389 adr x15, spci_smc_handler 390 adr x16, sprt_smc_handler 391 csel x15, x15, x16, ne 392 b prepare_enter_handler 393#else 394 b smc_unknown 395#endif 396 397compat_or_vendor: 398 399 /* Namespace is b'00 (compatibility) or b'01 (vendor) */ 400 401 /* 402 * Add the LSB of the namespace (bit [28]) to the OEN [27:24] to create 403 * a 5-bit index into the rt_svc_descs_indices array. 404 * 405 * The low 16 entries of the rt_svc_descs_indices array correspond to 406 * OENs of the compatibility namespace and the top 16 entries of the 407 * array are assigned to the vendor namespace descriptor. 408 */ 409 ubfx x16, x0, #FUNCID_OEN_SHIFT, #(FUNCID_OEN_WIDTH + 1) 410 411 load_rt_svc_desc_pointer 412 413prepare_enter_handler: 414 415#endif /* SMCCC_MAJOR_VERSION */ 416 417 /* 418 * Restore the saved C runtime stack value which will become the new 419 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 420 * structure prior to the last ERET from EL3. 421 */ 422 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 423 424 /* Switch to SP_EL0 */ 425 msr spsel, #0 426 427 /* 428 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 429 * switch during SMC handling. 430 * TODO: Revisit if all system registers can be saved later. 431 */ 432 mrs x16, spsr_el3 433 mrs x17, elr_el3 434 mrs x18, scr_el3 435 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 436 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 437 438 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 439 bfi x7, x18, #0, #1 440 441 mov sp, x12 442 443 /* 444 * Call the Secure Monitor Call handler and then drop directly into 445 * el3_exit() which will program any remaining architectural state 446 * prior to issuing the ERET to the desired lower EL. 447 */ 448#if DEBUG 449 cbz x15, rt_svc_fw_critical_error 450#endif 451 blr x15 452 453 b el3_exit 454 455smc_unknown: 456 /* 457 * Unknown SMC call. Populate return value with SMC_UNK, restore 458 * GP registers, and return to caller. 459 */ 460 mov x0, #SMC_UNK 461 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 462 b restore_gp_registers_eret 463 464smc_prohibited: 465 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 466 mov x0, #SMC_UNK 467 eret 468 469rt_svc_fw_critical_error: 470 /* Switch to SP_ELx */ 471 msr spsel, #1 472 no_ret report_unhandled_exception 473endfunc smc_handler 474