1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_data.h> 11#include <interrupt_mgmt.h> 12#include <platform_def.h> 13#include <runtime_svc.h> 14 15 .globl runtime_exceptions 16 17 .globl sync_exception_sp_el0 18 .globl irq_sp_el0 19 .globl fiq_sp_el0 20 .globl serror_sp_el0 21 22 .globl sync_exception_sp_elx 23 .globl irq_sp_elx 24 .globl fiq_sp_elx 25 .globl serror_sp_elx 26 27 .globl sync_exception_aarch64 28 .globl irq_aarch64 29 .globl fiq_aarch64 30 .globl serror_aarch64 31 32 .globl sync_exception_aarch32 33 .globl irq_aarch32 34 .globl fiq_aarch32 35 .globl serror_aarch32 36 37 /* --------------------------------------------------------------------- 38 * This macro handles Synchronous exceptions. 39 * Only SMC exceptions are supported. 40 * --------------------------------------------------------------------- 41 */ 42 .macro handle_sync_exception 43 /* Enable the SError interrupt */ 44 msr daifclr, #DAIF_ABT_BIT 45 46 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 47 48#if ENABLE_RUNTIME_INSTRUMENTATION 49 /* 50 * Read the timestamp value and store it in per-cpu data. The value 51 * will be extracted from per-cpu data by the C level SMC handler and 52 * saved to the PMF timestamp region. 53 */ 54 mrs x30, cntpct_el0 55 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 56 mrs x29, tpidr_el3 57 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 58 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 59#endif 60 61 mrs x30, esr_el3 62 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 63 64 /* Handle SMC exceptions separately from other synchronous exceptions */ 65 cmp x30, #EC_AARCH32_SMC 66 b.eq smc_handler32 67 68 cmp x30, #EC_AARCH64_SMC 69 b.eq smc_handler64 70 71 /* Other kinds of synchronous exceptions are not handled */ 72 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 73 b report_unhandled_exception 74 .endm 75 76 77 /* --------------------------------------------------------------------- 78 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 79 * interrupts. 80 * --------------------------------------------------------------------- 81 */ 82 .macro handle_interrupt_exception label 83 /* Enable the SError interrupt */ 84 msr daifclr, #DAIF_ABT_BIT 85 86 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 87 bl save_gp_registers 88 89 /* Save the EL3 system registers needed to return from this exception */ 90 mrs x0, spsr_el3 91 mrs x1, elr_el3 92 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 93 94 /* Switch to the runtime stack i.e. SP_EL0 */ 95 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 96 mov x20, sp 97 msr spsel, #0 98 mov sp, x2 99 100 /* 101 * Find out whether this is a valid interrupt type. 102 * If the interrupt controller reports a spurious interrupt then return 103 * to where we came from. 104 */ 105 bl plat_ic_get_pending_interrupt_type 106 cmp x0, #INTR_TYPE_INVAL 107 b.eq interrupt_exit_\label 108 109 /* 110 * Get the registered handler for this interrupt type. 111 * A NULL return value could be 'cause of the following conditions: 112 * 113 * a. An interrupt of a type was routed correctly but a handler for its 114 * type was not registered. 115 * 116 * b. An interrupt of a type was not routed correctly so a handler for 117 * its type was not registered. 118 * 119 * c. An interrupt of a type was routed correctly to EL3, but was 120 * deasserted before its pending state could be read. Another 121 * interrupt of a different type pended at the same time and its 122 * type was reported as pending instead. However, a handler for this 123 * type was not registered. 124 * 125 * a. and b. can only happen due to a programming error. The 126 * occurrence of c. could be beyond the control of Trusted Firmware. 127 * It makes sense to return from this exception instead of reporting an 128 * error. 129 */ 130 bl get_interrupt_type_handler 131 cbz x0, interrupt_exit_\label 132 mov x21, x0 133 134 mov x0, #INTR_ID_UNAVAILABLE 135 136 /* Set the current security state in the 'flags' parameter */ 137 mrs x2, scr_el3 138 ubfx x1, x2, #0, #1 139 140 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 141 mov x2, x20 142 143 /* x3 will point to a cookie (not used now) */ 144 mov x3, xzr 145 146 /* Call the interrupt type handler */ 147 blr x21 148 149interrupt_exit_\label: 150 /* Return from exception, possibly in a different security state */ 151 b el3_exit 152 153 .endm 154 155 156 .macro save_x18_to_x29_sp_el0 157 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 158 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 159 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 160 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 161 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 162 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 163 mrs x18, sp_el0 164 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 165 .endm 166 167 168vector_base runtime_exceptions 169 170 /* --------------------------------------------------------------------- 171 * Current EL with SP_EL0 : 0x0 - 0x200 172 * --------------------------------------------------------------------- 173 */ 174vector_entry sync_exception_sp_el0 175 /* We don't expect any synchronous exceptions from EL3 */ 176 b report_unhandled_exception 177 check_vector_size sync_exception_sp_el0 178 179vector_entry irq_sp_el0 180 /* 181 * EL3 code is non-reentrant. Any asynchronous exception is a serious 182 * error. Loop infinitely. 183 */ 184 b report_unhandled_interrupt 185 check_vector_size irq_sp_el0 186 187 188vector_entry fiq_sp_el0 189 b report_unhandled_interrupt 190 check_vector_size fiq_sp_el0 191 192 193vector_entry serror_sp_el0 194 b report_unhandled_exception 195 check_vector_size serror_sp_el0 196 197 /* --------------------------------------------------------------------- 198 * Current EL with SP_ELx: 0x200 - 0x400 199 * --------------------------------------------------------------------- 200 */ 201vector_entry sync_exception_sp_elx 202 /* 203 * This exception will trigger if anything went wrong during a previous 204 * exception entry or exit or while handling an earlier unexpected 205 * synchronous exception. There is a high probability that SP_EL3 is 206 * corrupted. 207 */ 208 b report_unhandled_exception 209 check_vector_size sync_exception_sp_elx 210 211vector_entry irq_sp_elx 212 b report_unhandled_interrupt 213 check_vector_size irq_sp_elx 214 215vector_entry fiq_sp_elx 216 b report_unhandled_interrupt 217 check_vector_size fiq_sp_elx 218 219vector_entry serror_sp_elx 220 b report_unhandled_exception 221 check_vector_size serror_sp_elx 222 223 /* --------------------------------------------------------------------- 224 * Lower EL using AArch64 : 0x400 - 0x600 225 * --------------------------------------------------------------------- 226 */ 227vector_entry sync_exception_aarch64 228 /* 229 * This exception vector will be the entry point for SMCs and traps 230 * that are unhandled at lower ELs most commonly. SP_EL3 should point 231 * to a valid cpu context where the general purpose and system register 232 * state can be saved. 233 */ 234 handle_sync_exception 235 check_vector_size sync_exception_aarch64 236 237vector_entry irq_aarch64 238 handle_interrupt_exception irq_aarch64 239 check_vector_size irq_aarch64 240 241vector_entry fiq_aarch64 242 handle_interrupt_exception fiq_aarch64 243 check_vector_size fiq_aarch64 244 245vector_entry serror_aarch64 246 /* 247 * SError exceptions from lower ELs are not currently supported. 248 * Report their occurrence. 249 */ 250 b report_unhandled_exception 251 check_vector_size serror_aarch64 252 253 /* --------------------------------------------------------------------- 254 * Lower EL using AArch32 : 0x600 - 0x800 255 * --------------------------------------------------------------------- 256 */ 257vector_entry sync_exception_aarch32 258 /* 259 * This exception vector will be the entry point for SMCs and traps 260 * that are unhandled at lower ELs most commonly. SP_EL3 should point 261 * to a valid cpu context where the general purpose and system register 262 * state can be saved. 263 */ 264 handle_sync_exception 265 check_vector_size sync_exception_aarch32 266 267vector_entry irq_aarch32 268 handle_interrupt_exception irq_aarch32 269 check_vector_size irq_aarch32 270 271vector_entry fiq_aarch32 272 handle_interrupt_exception fiq_aarch32 273 check_vector_size fiq_aarch32 274 275vector_entry serror_aarch32 276 /* 277 * SError exceptions from lower ELs are not currently supported. 278 * Report their occurrence. 279 */ 280 b report_unhandled_exception 281 check_vector_size serror_aarch32 282 283 284 /* --------------------------------------------------------------------- 285 * The following code handles secure monitor calls. 286 * Depending upon the execution state from where the SMC has been 287 * invoked, it frees some general purpose registers to perform the 288 * remaining tasks. They involve finding the runtime service handler 289 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 290 * before calling the handler. 291 * 292 * Note that x30 has been explicitly saved and can be used here 293 * --------------------------------------------------------------------- 294 */ 295func smc_handler 296smc_handler32: 297 /* Check whether aarch32 issued an SMC64 */ 298 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 299 300 /* 301 * Since we're are coming from aarch32, x8-x18 need to be saved as per 302 * SMC32 calling convention. If a lower EL in aarch64 is making an 303 * SMC32 call then it must have saved x8-x17 already therein. 304 */ 305 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 306 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 307 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 308 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 309 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 310 311 /* x4-x7, x18, sp_el0 are saved below */ 312 313smc_handler64: 314 /* 315 * Populate the parameters for the SMC handler. 316 * We already have x0-x4 in place. x5 will point to a cookie (not used 317 * now). x6 will point to the context structure (SP_EL3) and x7 will 318 * contain flags we need to pass to the handler Hence save x5-x7. 319 * 320 * Note: x4 only needs to be preserved for AArch32 callers but we do it 321 * for AArch64 callers as well for convenience 322 */ 323 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 324 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 325 326 /* Save rest of the gpregs and sp_el0*/ 327 save_x18_to_x29_sp_el0 328 329 mov x5, xzr 330 mov x6, sp 331 332 /* Get the unique owning entity number */ 333 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 334 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 335 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 336 337 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 338 339 /* Load descriptor index from array of indices */ 340 adr x14, rt_svc_descs_indices 341 ldrb w15, [x14, x16] 342 343 /* 344 * Restore the saved C runtime stack value which will become the new 345 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 346 * structure prior to the last ERET from EL3. 347 */ 348 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 349 350 /* 351 * Any index greater than 127 is invalid. Check bit 7 for 352 * a valid index 353 */ 354 tbnz w15, 7, smc_unknown 355 356 /* Switch to SP_EL0 */ 357 msr spsel, #0 358 359 /* 360 * Get the descriptor using the index 361 * x11 = (base + off), x15 = index 362 * 363 * handler = (base + off) + (index << log2(size)) 364 */ 365 lsl w10, w15, #RT_SVC_SIZE_LOG2 366 ldr x15, [x11, w10, uxtw] 367 368 /* 369 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 370 * switch during SMC handling. 371 * TODO: Revisit if all system registers can be saved later. 372 */ 373 mrs x16, spsr_el3 374 mrs x17, elr_el3 375 mrs x18, scr_el3 376 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 377 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 378 379 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 380 bfi x7, x18, #0, #1 381 382 mov sp, x12 383 384 /* 385 * Call the Secure Monitor Call handler and then drop directly into 386 * el3_exit() which will program any remaining architectural state 387 * prior to issuing the ERET to the desired lower EL. 388 */ 389#if DEBUG 390 cbz x15, rt_svc_fw_critical_error 391#endif 392 blr x15 393 394 b el3_exit 395 396smc_unknown: 397 /* 398 * Here we restore x4-x18 regardless of where we came from. AArch32 399 * callers will find the registers contents unchanged, but AArch64 400 * callers will find the registers modified (with stale earlier NS 401 * content). Either way, we aren't leaking any secure information 402 * through them. 403 */ 404 mov w0, #SMC_UNK 405 b restore_gp_registers_callee_eret 406 407smc_prohibited: 408 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 409 mov w0, #SMC_UNK 410 eret 411 412rt_svc_fw_critical_error: 413 /* Switch to SP_ELx */ 414 msr spsel, #1 415 no_ret report_unhandled_exception 416endfunc smc_handler 417