1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_data.h> 11#include <interrupt_mgmt.h> 12#include <platform_def.h> 13#include <runtime_svc.h> 14 15 .globl runtime_exceptions 16 17 .globl sync_exception_sp_el0 18 .globl irq_sp_el0 19 .globl fiq_sp_el0 20 .globl serror_sp_el0 21 22 .globl sync_exception_sp_elx 23 .globl irq_sp_elx 24 .globl fiq_sp_elx 25 .globl serror_sp_elx 26 27 .globl sync_exception_aarch64 28 .globl irq_aarch64 29 .globl fiq_aarch64 30 .globl serror_aarch64 31 32 .globl sync_exception_aarch32 33 .globl irq_aarch32 34 .globl fiq_aarch32 35 .globl serror_aarch32 36 37 /* --------------------------------------------------------------------- 38 * This macro handles Synchronous exceptions. 39 * Only SMC exceptions are supported. 40 * --------------------------------------------------------------------- 41 */ 42 .macro handle_sync_exception 43 /* Enable the SError interrupt */ 44 msr daifclr, #DAIF_ABT_BIT 45 46 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 47 48#if ENABLE_RUNTIME_INSTRUMENTATION 49 /* 50 * Read the timestamp value and store it in per-cpu data. The value 51 * will be extracted from per-cpu data by the C level SMC handler and 52 * saved to the PMF timestamp region. 53 */ 54 mrs x30, cntpct_el0 55 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 56 mrs x29, tpidr_el3 57 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 58 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 59#endif 60 61 mrs x30, esr_el3 62 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 63 64 /* Handle SMC exceptions separately from other synchronous exceptions */ 65 cmp x30, #EC_AARCH32_SMC 66 b.eq smc_handler32 67 68 cmp x30, #EC_AARCH64_SMC 69 b.eq smc_handler64 70 71 /* Other kinds of synchronous exceptions are not handled */ 72 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 73 b report_unhandled_exception 74 .endm 75 76 77 /* --------------------------------------------------------------------- 78 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 79 * interrupts. 80 * --------------------------------------------------------------------- 81 */ 82 .macro handle_interrupt_exception label 83 /* Enable the SError interrupt */ 84 msr daifclr, #DAIF_ABT_BIT 85 86 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 87 bl save_gp_registers 88 89 /* Save the EL3 system registers needed to return from this exception */ 90 mrs x0, spsr_el3 91 mrs x1, elr_el3 92 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 93 94 /* Switch to the runtime stack i.e. SP_EL0 */ 95 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 96 mov x20, sp 97 msr spsel, #0 98 mov sp, x2 99 100 /* 101 * Find out whether this is a valid interrupt type. 102 * If the interrupt controller reports a spurious interrupt then return 103 * to where we came from. 104 */ 105 bl plat_ic_get_pending_interrupt_type 106 cmp x0, #INTR_TYPE_INVAL 107 b.eq interrupt_exit_\label 108 109 /* 110 * Get the registered handler for this interrupt type. 111 * A NULL return value could be 'cause of the following conditions: 112 * 113 * a. An interrupt of a type was routed correctly but a handler for its 114 * type was not registered. 115 * 116 * b. An interrupt of a type was not routed correctly so a handler for 117 * its type was not registered. 118 * 119 * c. An interrupt of a type was routed correctly to EL3, but was 120 * deasserted before its pending state could be read. Another 121 * interrupt of a different type pended at the same time and its 122 * type was reported as pending instead. However, a handler for this 123 * type was not registered. 124 * 125 * a. and b. can only happen due to a programming error. The 126 * occurrence of c. could be beyond the control of Trusted Firmware. 127 * It makes sense to return from this exception instead of reporting an 128 * error. 129 */ 130 bl get_interrupt_type_handler 131 cbz x0, interrupt_exit_\label 132 mov x21, x0 133 134 mov x0, #INTR_ID_UNAVAILABLE 135 136 /* Set the current security state in the 'flags' parameter */ 137 mrs x2, scr_el3 138 ubfx x1, x2, #0, #1 139 140 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 141 mov x2, x20 142 143 /* x3 will point to a cookie (not used now) */ 144 mov x3, xzr 145 146 /* Call the interrupt type handler */ 147 blr x21 148 149interrupt_exit_\label: 150 /* Return from exception, possibly in a different security state */ 151 b el3_exit 152 153 .endm 154 155 156 .macro save_x4_to_x29_sp_el0 157 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 158 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 159 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 160 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 161 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 162 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 163 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 164 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 165 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 166 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 167 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 168 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 169 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 170 mrs x18, sp_el0 171 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 172 .endm 173 174 175vector_base runtime_exceptions 176 177 /* --------------------------------------------------------------------- 178 * Current EL with SP_EL0 : 0x0 - 0x200 179 * --------------------------------------------------------------------- 180 */ 181vector_entry sync_exception_sp_el0 182 /* We don't expect any synchronous exceptions from EL3 */ 183 b report_unhandled_exception 184 check_vector_size sync_exception_sp_el0 185 186vector_entry irq_sp_el0 187 /* 188 * EL3 code is non-reentrant. Any asynchronous exception is a serious 189 * error. Loop infinitely. 190 */ 191 b report_unhandled_interrupt 192 check_vector_size irq_sp_el0 193 194 195vector_entry fiq_sp_el0 196 b report_unhandled_interrupt 197 check_vector_size fiq_sp_el0 198 199 200vector_entry serror_sp_el0 201 b report_unhandled_exception 202 check_vector_size serror_sp_el0 203 204 /* --------------------------------------------------------------------- 205 * Current EL with SP_ELx: 0x200 - 0x400 206 * --------------------------------------------------------------------- 207 */ 208vector_entry sync_exception_sp_elx 209 /* 210 * This exception will trigger if anything went wrong during a previous 211 * exception entry or exit or while handling an earlier unexpected 212 * synchronous exception. There is a high probability that SP_EL3 is 213 * corrupted. 214 */ 215 b report_unhandled_exception 216 check_vector_size sync_exception_sp_elx 217 218vector_entry irq_sp_elx 219 b report_unhandled_interrupt 220 check_vector_size irq_sp_elx 221 222vector_entry fiq_sp_elx 223 b report_unhandled_interrupt 224 check_vector_size fiq_sp_elx 225 226vector_entry serror_sp_elx 227 b report_unhandled_exception 228 check_vector_size serror_sp_elx 229 230 /* --------------------------------------------------------------------- 231 * Lower EL using AArch64 : 0x400 - 0x600 232 * --------------------------------------------------------------------- 233 */ 234vector_entry sync_exception_aarch64 235 /* 236 * This exception vector will be the entry point for SMCs and traps 237 * that are unhandled at lower ELs most commonly. SP_EL3 should point 238 * to a valid cpu context where the general purpose and system register 239 * state can be saved. 240 */ 241 handle_sync_exception 242 check_vector_size sync_exception_aarch64 243 244vector_entry irq_aarch64 245 handle_interrupt_exception irq_aarch64 246 check_vector_size irq_aarch64 247 248vector_entry fiq_aarch64 249 handle_interrupt_exception fiq_aarch64 250 check_vector_size fiq_aarch64 251 252vector_entry serror_aarch64 253 /* 254 * SError exceptions from lower ELs are not currently supported. 255 * Report their occurrence. 256 */ 257 b report_unhandled_exception 258 check_vector_size serror_aarch64 259 260 /* --------------------------------------------------------------------- 261 * Lower EL using AArch32 : 0x600 - 0x800 262 * --------------------------------------------------------------------- 263 */ 264vector_entry sync_exception_aarch32 265 /* 266 * This exception vector will be the entry point for SMCs and traps 267 * that are unhandled at lower ELs most commonly. SP_EL3 should point 268 * to a valid cpu context where the general purpose and system register 269 * state can be saved. 270 */ 271 handle_sync_exception 272 check_vector_size sync_exception_aarch32 273 274vector_entry irq_aarch32 275 handle_interrupt_exception irq_aarch32 276 check_vector_size irq_aarch32 277 278vector_entry fiq_aarch32 279 handle_interrupt_exception fiq_aarch32 280 check_vector_size fiq_aarch32 281 282vector_entry serror_aarch32 283 /* 284 * SError exceptions from lower ELs are not currently supported. 285 * Report their occurrence. 286 */ 287 b report_unhandled_exception 288 check_vector_size serror_aarch32 289 290 291 /* --------------------------------------------------------------------- 292 * The following code handles secure monitor calls. 293 * Depending upon the execution state from where the SMC has been 294 * invoked, it frees some general purpose registers to perform the 295 * remaining tasks. They involve finding the runtime service handler 296 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 297 * before calling the handler. 298 * 299 * Note that x30 has been explicitly saved and can be used here 300 * --------------------------------------------------------------------- 301 */ 302func smc_handler 303smc_handler32: 304 /* Check whether aarch32 issued an SMC64 */ 305 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 306 307smc_handler64: 308 /* 309 * Populate the parameters for the SMC handler. 310 * We already have x0-x4 in place. x5 will point to a cookie (not used 311 * now). x6 will point to the context structure (SP_EL3) and x7 will 312 * contain flags we need to pass to the handler. 313 * 314 * Save x4-x29 and sp_el0. Refer to SMCCC v1.1. 315 */ 316 save_x4_to_x29_sp_el0 317 318 mov x5, xzr 319 mov x6, sp 320 321 /* Get the unique owning entity number */ 322 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 323 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 324 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 325 326 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 327 328 /* Load descriptor index from array of indices */ 329 adr x14, rt_svc_descs_indices 330 ldrb w15, [x14, x16] 331 332 /* 333 * Restore the saved C runtime stack value which will become the new 334 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 335 * structure prior to the last ERET from EL3. 336 */ 337 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 338 339 /* 340 * Any index greater than 127 is invalid. Check bit 7 for 341 * a valid index 342 */ 343 tbnz w15, 7, smc_unknown 344 345 /* Switch to SP_EL0 */ 346 msr spsel, #0 347 348 /* 349 * Get the descriptor using the index 350 * x11 = (base + off), x15 = index 351 * 352 * handler = (base + off) + (index << log2(size)) 353 */ 354 lsl w10, w15, #RT_SVC_SIZE_LOG2 355 ldr x15, [x11, w10, uxtw] 356 357 /* 358 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 359 * switch during SMC handling. 360 * TODO: Revisit if all system registers can be saved later. 361 */ 362 mrs x16, spsr_el3 363 mrs x17, elr_el3 364 mrs x18, scr_el3 365 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 366 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 367 368 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 369 bfi x7, x18, #0, #1 370 371 mov sp, x12 372 373 /* 374 * Call the Secure Monitor Call handler and then drop directly into 375 * el3_exit() which will program any remaining architectural state 376 * prior to issuing the ERET to the desired lower EL. 377 */ 378#if DEBUG 379 cbz x15, rt_svc_fw_critical_error 380#endif 381 blr x15 382 383 b el3_exit 384 385smc_unknown: 386 /* 387 * Here we restore x4-x18 regardless of where we came from. AArch32 388 * callers will find the registers contents unchanged, but AArch64 389 * callers will find the registers modified (with stale earlier NS 390 * content). Either way, we aren't leaking any secure information 391 * through them. 392 */ 393 mov x0, #SMC_UNK 394 b restore_gp_registers_callee_eret 395 396smc_prohibited: 397 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 398 mov x0, #SMC_UNK 399 eret 400 401rt_svc_fw_critical_error: 402 /* Switch to SP_ELx */ 403 msr spsel, #1 404 no_ret report_unhandled_exception 405endfunc smc_handler 406