1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <context.h> 34#include <cpu_data.h> 35#include <interrupt_mgmt.h> 36#include <platform_def.h> 37#include <runtime_svc.h> 38 39 .globl runtime_exceptions 40 41 /* ----------------------------------------------------- 42 * Handle SMC exceptions separately from other sync. 43 * exceptions. 44 * ----------------------------------------------------- 45 */ 46 .macro handle_sync_exception 47 /* Enable the SError interrupt */ 48 msr daifclr, #DAIF_ABT_BIT 49 50 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 51 52#if ENABLE_RUNTIME_INSTRUMENTATION 53 54 /* 55 * Read the timestamp value and store it in per-cpu data. 56 * The value will be extracted from per-cpu data by the 57 * C level SMC handler and saved to the PMF timestamp region. 58 */ 59 mrs x30, cntpct_el0 60 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 61 mrs x29, tpidr_el3 62 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 63 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 64#endif 65 66 mrs x30, esr_el3 67 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 68 69 cmp x30, #EC_AARCH32_SMC 70 b.eq smc_handler32 71 72 cmp x30, #EC_AARCH64_SMC 73 b.eq smc_handler64 74 75 /* ----------------------------------------------------- 76 * The following code handles any synchronous exception 77 * that is not an SMC. 78 * ----------------------------------------------------- 79 */ 80 81 bl report_unhandled_exception 82 .endm 83 84 85 /* ----------------------------------------------------- 86 * This macro handles FIQ or IRQ interrupts i.e. EL3, 87 * S-EL1 and NS interrupts. 88 * ----------------------------------------------------- 89 */ 90 .macro handle_interrupt_exception label 91 /* Enable the SError interrupt */ 92 msr daifclr, #DAIF_ABT_BIT 93 94 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 95 bl save_gp_registers 96 97 /* 98 * Save the EL3 system registers needed to return from 99 * this exception. 100 */ 101 mrs x0, spsr_el3 102 mrs x1, elr_el3 103 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 104 105 /* Switch to the runtime stack i.e. SP_EL0 */ 106 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 107 mov x20, sp 108 msr spsel, #0 109 mov sp, x2 110 111 /* 112 * Find out whether this is a valid interrupt type. If the 113 * interrupt controller reports a spurious interrupt then 114 * return to where we came from. 115 */ 116 bl plat_ic_get_pending_interrupt_type 117 cmp x0, #INTR_TYPE_INVAL 118 b.eq interrupt_exit_\label 119 120 /* 121 * Get the registered handler for this interrupt type. A 122 * NULL return value could be 'cause of the following 123 * conditions: 124 * 125 * a. An interrupt of a type was routed correctly but a 126 * handler for its type was not registered. 127 * 128 * b. An interrupt of a type was not routed correctly so 129 * a handler for its type was not registered. 130 * 131 * c. An interrupt of a type was routed correctly to EL3, 132 * but was deasserted before its pending state could 133 * be read. Another interrupt of a different type pended 134 * at the same time and its type was reported as pending 135 * instead. However, a handler for this type was not 136 * registered. 137 * 138 * a. and b. can only happen due to a programming error. 139 * The occurrence of c. could be beyond the control of 140 * Trusted Firmware. It makes sense to return from this 141 * exception instead of reporting an error. 142 */ 143 bl get_interrupt_type_handler 144 cbz x0, interrupt_exit_\label 145 mov x21, x0 146 147 mov x0, #INTR_ID_UNAVAILABLE 148 149 /* Set the current security state in the 'flags' parameter */ 150 mrs x2, scr_el3 151 ubfx x1, x2, #0, #1 152 153 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 154 mov x2, x20 155 156 /* x3 will point to a cookie (not used now) */ 157 mov x3, xzr 158 159 /* Call the interrupt type handler */ 160 blr x21 161 162interrupt_exit_\label: 163 /* Return from exception, possibly in a different security state */ 164 b el3_exit 165 166 .endm 167 168 169 .macro save_x18_to_x29_sp_el0 170 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 171 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 172 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 173 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 174 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 175 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 176 mrs x18, sp_el0 177 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 178 .endm 179 180 181vector_base runtime_exceptions 182 183 /* ----------------------------------------------------- 184 * Current EL with _sp_el0 : 0x0 - 0x200 185 * ----------------------------------------------------- 186 */ 187vector_entry sync_exception_sp_el0 188 /* ----------------------------------------------------- 189 * We don't expect any synchronous exceptions from EL3 190 * ----------------------------------------------------- 191 */ 192 bl report_unhandled_exception 193 check_vector_size sync_exception_sp_el0 194 195 /* ----------------------------------------------------- 196 * EL3 code is non-reentrant. Any asynchronous exception 197 * is a serious error. Loop infinitely. 198 * ----------------------------------------------------- 199 */ 200vector_entry irq_sp_el0 201 bl report_unhandled_interrupt 202 check_vector_size irq_sp_el0 203 204 205vector_entry fiq_sp_el0 206 bl report_unhandled_interrupt 207 check_vector_size fiq_sp_el0 208 209 210vector_entry serror_sp_el0 211 bl report_unhandled_exception 212 check_vector_size serror_sp_el0 213 214 /* ----------------------------------------------------- 215 * Current EL with SPx: 0x200 - 0x400 216 * ----------------------------------------------------- 217 */ 218 219vector_entry sync_exception_sp_elx 220 /* ----------------------------------------------------- 221 * This exception will trigger if anything went wrong 222 * during a previous exception entry or exit or while 223 * handling an earlier unexpected synchronous exception. 224 * There is a high probability that SP_EL3 is corrupted. 225 * ----------------------------------------------------- 226 */ 227 bl report_unhandled_exception 228 check_vector_size sync_exception_sp_elx 229 230vector_entry irq_sp_elx 231 bl report_unhandled_interrupt 232 check_vector_size irq_sp_elx 233 234vector_entry fiq_sp_elx 235 bl report_unhandled_interrupt 236 check_vector_size fiq_sp_elx 237 238vector_entry serror_sp_elx 239 bl report_unhandled_exception 240 check_vector_size serror_sp_elx 241 242 /* ----------------------------------------------------- 243 * Lower EL using AArch64 : 0x400 - 0x600 244 * ----------------------------------------------------- 245 */ 246vector_entry sync_exception_aarch64 247 /* ----------------------------------------------------- 248 * This exception vector will be the entry point for 249 * SMCs and traps that are unhandled at lower ELs most 250 * commonly. SP_EL3 should point to a valid cpu context 251 * where the general purpose and system register state 252 * can be saved. 253 * ----------------------------------------------------- 254 */ 255 handle_sync_exception 256 check_vector_size sync_exception_aarch64 257 258 /* ----------------------------------------------------- 259 * Asynchronous exceptions from lower ELs are not 260 * currently supported. Report their occurrence. 261 * ----------------------------------------------------- 262 */ 263vector_entry irq_aarch64 264 handle_interrupt_exception irq_aarch64 265 check_vector_size irq_aarch64 266 267vector_entry fiq_aarch64 268 handle_interrupt_exception fiq_aarch64 269 check_vector_size fiq_aarch64 270 271vector_entry serror_aarch64 272 bl report_unhandled_exception 273 check_vector_size serror_aarch64 274 275 /* ----------------------------------------------------- 276 * Lower EL using AArch32 : 0x600 - 0x800 277 * ----------------------------------------------------- 278 */ 279vector_entry sync_exception_aarch32 280 /* ----------------------------------------------------- 281 * This exception vector will be the entry point for 282 * SMCs and traps that are unhandled at lower ELs most 283 * commonly. SP_EL3 should point to a valid cpu context 284 * where the general purpose and system register state 285 * can be saved. 286 * ----------------------------------------------------- 287 */ 288 handle_sync_exception 289 check_vector_size sync_exception_aarch32 290 291 /* ----------------------------------------------------- 292 * Asynchronous exceptions from lower ELs are not 293 * currently supported. Report their occurrence. 294 * ----------------------------------------------------- 295 */ 296vector_entry irq_aarch32 297 handle_interrupt_exception irq_aarch32 298 check_vector_size irq_aarch32 299 300vector_entry fiq_aarch32 301 handle_interrupt_exception fiq_aarch32 302 check_vector_size fiq_aarch32 303 304vector_entry serror_aarch32 305 bl report_unhandled_exception 306 check_vector_size serror_aarch32 307 308 309 /* ----------------------------------------------------- 310 * The following code handles secure monitor calls. 311 * Depending upon the execution state from where the SMC 312 * has been invoked, it frees some general purpose 313 * registers to perform the remaining tasks. They 314 * involve finding the runtime service handler that is 315 * the target of the SMC & switching to runtime stacks 316 * (SP_EL0) before calling the handler. 317 * 318 * Note that x30 has been explicitly saved and can be 319 * used here 320 * ----------------------------------------------------- 321 */ 322func smc_handler 323smc_handler32: 324 /* Check whether aarch32 issued an SMC64 */ 325 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 326 327 /* ----------------------------------------------------- 328 * Since we're are coming from aarch32, x8-x18 need to 329 * be saved as per SMC32 calling convention. If a lower 330 * EL in aarch64 is making an SMC32 call then it must 331 * have saved x8-x17 already therein. 332 * ----------------------------------------------------- 333 */ 334 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 335 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 336 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 337 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 338 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 339 340 /* x4-x7, x18, sp_el0 are saved below */ 341 342smc_handler64: 343 /* ----------------------------------------------------- 344 * Populate the parameters for the SMC handler. We 345 * already have x0-x4 in place. x5 will point to a 346 * cookie (not used now). x6 will point to the context 347 * structure (SP_EL3) and x7 will contain flags we need 348 * to pass to the handler Hence save x5-x7. Note that x4 349 * only needs to be preserved for AArch32 callers but we 350 * do it for AArch64 callers as well for convenience 351 * ----------------------------------------------------- 352 */ 353 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 354 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 355 356 /* Save rest of the gpregs and sp_el0*/ 357 save_x18_to_x29_sp_el0 358 359 mov x5, xzr 360 mov x6, sp 361 362 /* Get the unique owning entity number */ 363 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 364 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 365 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 366 367 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 368 369 /* Load descriptor index from array of indices */ 370 adr x14, rt_svc_descs_indices 371 ldrb w15, [x14, x16] 372 373 /* ----------------------------------------------------- 374 * Restore the saved C runtime stack value which will 375 * become the new SP_EL0 i.e. EL3 runtime stack. It was 376 * saved in the 'cpu_context' structure prior to the last 377 * ERET from EL3. 378 * ----------------------------------------------------- 379 */ 380 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 381 382 /* 383 * Any index greater than 127 is invalid. Check bit 7 for 384 * a valid index 385 */ 386 tbnz w15, 7, smc_unknown 387 388 /* Switch to SP_EL0 */ 389 msr spsel, #0 390 391 /* ----------------------------------------------------- 392 * Get the descriptor using the index 393 * x11 = (base + off), x15 = index 394 * 395 * handler = (base + off) + (index << log2(size)) 396 * ----------------------------------------------------- 397 */ 398 lsl w10, w15, #RT_SVC_SIZE_LOG2 399 ldr x15, [x11, w10, uxtw] 400 401 /* ----------------------------------------------------- 402 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 403 * is a world switch during SMC handling. 404 * TODO: Revisit if all system registers can be saved 405 * later. 406 * ----------------------------------------------------- 407 */ 408 mrs x16, spsr_el3 409 mrs x17, elr_el3 410 mrs x18, scr_el3 411 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 412 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 413 414 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 415 bfi x7, x18, #0, #1 416 417 mov sp, x12 418 419 /* ----------------------------------------------------- 420 * Call the Secure Monitor Call handler and then drop 421 * directly into el3_exit() which will program any 422 * remaining architectural state prior to issuing the 423 * ERET to the desired lower EL. 424 * ----------------------------------------------------- 425 */ 426#if DEBUG 427 cbz x15, rt_svc_fw_critical_error 428#endif 429 blr x15 430 431 b el3_exit 432 433smc_unknown: 434 /* 435 * Here we restore x4-x18 regardless of where we came from. AArch32 436 * callers will find the registers contents unchanged, but AArch64 437 * callers will find the registers modified (with stale earlier NS 438 * content). Either way, we aren't leaking any secure information 439 * through them 440 */ 441 mov w0, #SMC_UNK 442 b restore_gp_registers_callee_eret 443 444smc_prohibited: 445 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 446 mov w0, #SMC_UNK 447 eret 448 449rt_svc_fw_critical_error: 450 msr spsel, #1 /* Switch to SP_ELx */ 451 bl report_unhandled_exception 452endfunc smc_handler 453