xref: /rk3399_ARM-atf/bl31/aarch64/runtime_exceptions.S (revision 7d37aa171158422b5ee7ee6c3cdad58f6aa066b4) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <context.h>
34#include <interrupt_mgmt.h>
35#include <platform_def.h>
36#include <runtime_svc.h>
37
38	.globl	runtime_exceptions
39	.globl	el3_exit
40
41	/* -----------------------------------------------------
42	 * Handle SMC exceptions separately from other sync.
43	 * exceptions.
44	 * -----------------------------------------------------
45	 */
46	.macro	handle_sync_exception
47	/* Enable the SError interrupt */
48	msr	daifclr, #DAIF_ABT_BIT
49
50	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
51	mrs	x30, esr_el3
52	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
53
54	cmp	x30, #EC_AARCH32_SMC
55	b.eq	smc_handler32
56
57	cmp	x30, #EC_AARCH64_SMC
58	b.eq	smc_handler64
59
60	/* -----------------------------------------------------
61	 * The following code handles any synchronous exception
62	 * that is not an SMC.
63	 * -----------------------------------------------------
64	 */
65
66	bl	report_unhandled_exception
67	.endm
68
69
70	/* -----------------------------------------------------
71	 * This macro handles FIQ or IRQ interrupts i.e. EL3,
72	 * S-EL1 and NS interrupts.
73	 * -----------------------------------------------------
74	 */
75	.macro	handle_interrupt_exception label
76	/* Enable the SError interrupt */
77	msr	daifclr, #DAIF_ABT_BIT
78
79	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
80	bl	save_gp_registers
81
82	/*
83	 * Save the EL3 system registers needed to return from
84	 * this exception.
85	 */
86	mrs	x0, spsr_el3
87	mrs	x1, elr_el3
88	stp	x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
89
90	/* Switch to the runtime stack i.e. SP_EL0 */
91	ldr	x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
92	mov	x20, sp
93	msr	spsel, #0
94	mov	sp, x2
95
96	/*
97	 * Find out whether this is a valid interrupt type. If the
98	 * interrupt controller reports a spurious interrupt then
99	 * return to where we came from.
100	 */
101	bl	plat_ic_get_pending_interrupt_type
102	cmp	x0, #INTR_TYPE_INVAL
103	b.eq	interrupt_exit_\label
104
105	/*
106	 * Get the registered handler for this interrupt type. A
107	 * NULL return value could be 'cause of the following
108	 * conditions:
109	 *
110	 * a. An interrupt of a type was routed correctly but a
111	 *    handler for its type was not registered.
112	 *
113	 * b. An interrupt of a type was not routed correctly so
114	 *    a handler for its type was not registered.
115	 *
116	 * c. An interrupt of a type was routed correctly to EL3,
117	 *    but was deasserted before its pending state could
118	 *    be read. Another interrupt of a different type pended
119	 *    at the same time and its type was reported as pending
120	 *    instead. However, a handler for this type was not
121	 *    registered.
122	 *
123	 * a. and b. can only happen due to a programming error.
124	 * The occurrence of c. could be beyond the control of
125	 * Trusted Firmware. It makes sense to return from this
126	 * exception instead of reporting an error.
127	 */
128	bl	get_interrupt_type_handler
129	cbz	x0, interrupt_exit_\label
130	mov	x21, x0
131
132	mov	x0, #INTR_ID_UNAVAILABLE
133#if IMF_READ_INTERRUPT_ID
134	/*
135	 * Read the id of the highest priority pending interrupt. If
136	 * no interrupt is asserted then return to where we came from.
137	 */
138	mov	x19,  #INTR_ID_UNAVAILABLE
139	bl	plat_ic_get_pending_interrupt_id
140	cmp	x19, x0
141	b.eq	interrupt_exit_\label
142#endif
143
144	/* Set the current security state in the 'flags' parameter */
145	mrs	x2, scr_el3
146	ubfx	x1, x2, #0, #1
147
148	/* Restore the reference to the 'handle' i.e. SP_EL3 */
149	mov	x2, x20
150
151	/*  x3 will point to a cookie (not used now) */
152	mov	x3, xzr
153
154	/* Call the interrupt type handler */
155	blr	x21
156
157interrupt_exit_\label:
158	/* Return from exception, possibly in a different security state */
159	b	el3_exit
160
161	.endm
162
163
164	.macro save_x18_to_x29_sp_el0
165	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
166	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
167	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
168	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
169	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
170	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
171	mrs	x18, sp_el0
172	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
173	.endm
174
175	.section	.vectors, "ax"; .align 11
176	.align	7
177runtime_exceptions:
178	/* -----------------------------------------------------
179	 * Current EL with _sp_el0 : 0x0 - 0x200
180	 * -----------------------------------------------------
181	 */
182sync_exception_sp_el0:
183	/* -----------------------------------------------------
184	 * We don't expect any synchronous exceptions from EL3
185	 * -----------------------------------------------------
186	 */
187	bl	report_unhandled_exception
188	check_vector_size sync_exception_sp_el0
189
190	.align	7
191	/* -----------------------------------------------------
192	 * EL3 code is non-reentrant. Any asynchronous exception
193	 * is a serious error. Loop infinitely.
194	 * -----------------------------------------------------
195	 */
196irq_sp_el0:
197	bl	report_unhandled_interrupt
198	check_vector_size irq_sp_el0
199
200	.align	7
201fiq_sp_el0:
202	bl	report_unhandled_interrupt
203	check_vector_size fiq_sp_el0
204
205	.align	7
206serror_sp_el0:
207	bl	report_unhandled_exception
208	check_vector_size serror_sp_el0
209
210	/* -----------------------------------------------------
211	 * Current EL with SPx: 0x200 - 0x400
212	 * -----------------------------------------------------
213	 */
214	.align	7
215sync_exception_sp_elx:
216	/* -----------------------------------------------------
217	 * This exception will trigger if anything went wrong
218	 * during a previous exception entry or exit or while
219	 * handling an earlier unexpected synchronous exception.
220	 * There is a high probability that SP_EL3 is corrupted.
221	 * -----------------------------------------------------
222	 */
223	bl	report_unhandled_exception
224	check_vector_size sync_exception_sp_elx
225
226	.align	7
227irq_sp_elx:
228	bl	report_unhandled_interrupt
229	check_vector_size irq_sp_elx
230
231	.align	7
232fiq_sp_elx:
233	bl	report_unhandled_interrupt
234	check_vector_size fiq_sp_elx
235
236	.align	7
237serror_sp_elx:
238	bl	report_unhandled_exception
239	check_vector_size serror_sp_elx
240
241	/* -----------------------------------------------------
242	 * Lower EL using AArch64 : 0x400 - 0x600
243	 * -----------------------------------------------------
244	 */
245	.align	7
246sync_exception_aarch64:
247	/* -----------------------------------------------------
248	 * This exception vector will be the entry point for
249	 * SMCs and traps that are unhandled at lower ELs most
250	 * commonly. SP_EL3 should point to a valid cpu context
251	 * where the general purpose and system register state
252	 * can be saved.
253	 * -----------------------------------------------------
254	 */
255	handle_sync_exception
256	check_vector_size sync_exception_aarch64
257
258	.align	7
259	/* -----------------------------------------------------
260	 * Asynchronous exceptions from lower ELs are not
261	 * currently supported. Report their occurrence.
262	 * -----------------------------------------------------
263	 */
264irq_aarch64:
265	handle_interrupt_exception irq_aarch64
266	check_vector_size irq_aarch64
267
268	.align	7
269fiq_aarch64:
270	handle_interrupt_exception fiq_aarch64
271	check_vector_size fiq_aarch64
272
273	.align	7
274serror_aarch64:
275	bl	report_unhandled_exception
276	check_vector_size serror_aarch64
277
278	/* -----------------------------------------------------
279	 * Lower EL using AArch32 : 0x600 - 0x800
280	 * -----------------------------------------------------
281	 */
282	.align	7
283sync_exception_aarch32:
284	/* -----------------------------------------------------
285	 * This exception vector will be the entry point for
286	 * SMCs and traps that are unhandled at lower ELs most
287	 * commonly. SP_EL3 should point to a valid cpu context
288	 * where the general purpose and system register state
289	 * can be saved.
290	 * -----------------------------------------------------
291	 */
292	handle_sync_exception
293	check_vector_size sync_exception_aarch32
294
295	.align	7
296	/* -----------------------------------------------------
297	 * Asynchronous exceptions from lower ELs are not
298	 * currently supported. Report their occurrence.
299	 * -----------------------------------------------------
300	 */
301irq_aarch32:
302	handle_interrupt_exception irq_aarch32
303	check_vector_size irq_aarch32
304
305	.align	7
306fiq_aarch32:
307	handle_interrupt_exception fiq_aarch32
308	check_vector_size fiq_aarch32
309
310	.align	7
311serror_aarch32:
312	bl	report_unhandled_exception
313	check_vector_size serror_aarch32
314
315	.align	7
316
317	/* -----------------------------------------------------
318	 * The following code handles secure monitor calls.
319	 * Depending upon the execution state from where the SMC
320	 * has been invoked, it frees some general purpose
321	 * registers to perform the remaining tasks. They
322	 * involve finding the runtime service handler that is
323	 * the target of the SMC & switching to runtime stacks
324	 * (SP_EL0) before calling the handler.
325	 *
326	 * Note that x30 has been explicitly saved and can be
327	 * used here
328	 * -----------------------------------------------------
329	 */
330func smc_handler
331smc_handler32:
332	/* Check whether aarch32 issued an SMC64 */
333	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
334
335	/* -----------------------------------------------------
336	 * Since we're are coming from aarch32, x8-x18 need to
337	 * be saved as per SMC32 calling convention. If a lower
338	 * EL in aarch64 is making an SMC32 call then it must
339	 * have saved x8-x17 already therein.
340	 * -----------------------------------------------------
341	 */
342	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
343	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
344	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
345	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
346	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
347
348	/* x4-x7, x18, sp_el0 are saved below */
349
350smc_handler64:
351	/* -----------------------------------------------------
352	 * Populate the parameters for the SMC handler. We
353	 * already have x0-x4 in place. x5 will point to a
354	 * cookie (not used now). x6 will point to the context
355	 * structure (SP_EL3) and x7 will contain flags we need
356	 * to pass to the handler Hence save x5-x7. Note that x4
357	 * only needs to be preserved for AArch32 callers but we
358	 * do it for AArch64 callers as well for convenience
359	 * -----------------------------------------------------
360	 */
361	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
362	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
363
364	/* Save rest of the gpregs and sp_el0*/
365	save_x18_to_x29_sp_el0
366
367	mov	x5, xzr
368	mov	x6, sp
369
370	/* Get the unique owning entity number */
371	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
372	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
373	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
374
375	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
376
377	/* Load descriptor index from array of indices */
378	adr	x14, rt_svc_descs_indices
379	ldrb	w15, [x14, x16]
380
381	/* -----------------------------------------------------
382	 * Restore the saved C runtime stack value which will
383	 * become the new SP_EL0 i.e. EL3 runtime stack. It was
384	 * saved in the 'cpu_context' structure prior to the last
385	 * ERET from EL3.
386	 * -----------------------------------------------------
387	 */
388	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
389
390	/*
391	 * Any index greater than 127 is invalid. Check bit 7 for
392	 * a valid index
393	 */
394	tbnz	w15, 7, smc_unknown
395
396	/* Switch to SP_EL0 */
397	msr	spsel, #0
398
399	/* -----------------------------------------------------
400	 * Get the descriptor using the index
401	 * x11 = (base + off), x15 = index
402	 *
403	 * handler = (base + off) + (index << log2(size))
404	 * -----------------------------------------------------
405	 */
406	lsl	w10, w15, #RT_SVC_SIZE_LOG2
407	ldr	x15, [x11, w10, uxtw]
408
409	/* -----------------------------------------------------
410	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
411	 * is a world switch during SMC handling.
412	 * TODO: Revisit if all system registers can be saved
413	 * later.
414	 * -----------------------------------------------------
415	 */
416	mrs	x16, spsr_el3
417	mrs	x17, elr_el3
418	mrs	x18, scr_el3
419	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
420	str	x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
421
422	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
423	bfi	x7, x18, #0, #1
424
425	mov	sp, x12
426
427	/* -----------------------------------------------------
428	 * Call the Secure Monitor Call handler and then drop
429	 * directly into el3_exit() which will program any
430	 * remaining architectural state prior to issuing the
431	 * ERET to the desired lower EL.
432	 * -----------------------------------------------------
433	 */
434#if DEBUG
435	cbz	x15, rt_svc_fw_critical_error
436#endif
437	blr	x15
438
439	/* -----------------------------------------------------
440	 * This routine assumes that the SP_EL3 is pointing to
441	 * a valid context structure from where the gp regs and
442	 * other special registers can be retrieved.
443	 *
444	 * Keep it in the same section as smc_handler as this
445	 * function uses a fall-through to el3_exit
446	 * -----------------------------------------------------
447	 */
448el3_exit: ; .type el3_exit, %function
449	/* -----------------------------------------------------
450	 * Save the current SP_EL0 i.e. the EL3 runtime stack
451	 * which will be used for handling the next SMC. Then
452	 * switch to SP_EL3
453	 * -----------------------------------------------------
454	 */
455	mov	x17, sp
456	msr	spsel, #1
457	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
458
459	/* -----------------------------------------------------
460	 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
461	 * -----------------------------------------------------
462	 */
463	ldr	x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
464	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
465	msr	scr_el3, x18
466	msr	spsr_el3, x16
467	msr	elr_el3, x17
468
469	/* Restore saved general purpose registers and return */
470	b	restore_gp_registers_eret
471
472smc_unknown:
473	/*
474	 * Here we restore x4-x18 regardless of where we came from. AArch32
475	 * callers will find the registers contents unchanged, but AArch64
476	 * callers will find the registers modified (with stale earlier NS
477	 * content). Either way, we aren't leaking any secure information
478	 * through them
479	 */
480	mov	w0, #SMC_UNK
481	b	restore_gp_registers_callee_eret
482
483smc_prohibited:
484	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
485	mov	w0, #SMC_UNK
486	eret
487
488rt_svc_fw_critical_error:
489	msr	spsel, #1 /* Switch to SP_ELx */
490	bl	report_unhandled_exception
491endfunc smc_handler
492
493	/* -----------------------------------------------------
494	 * The following functions are used to saved and restore
495	 * all the general pupose registers. Ideally we would
496	 * only save and restore the callee saved registers when
497	 * a world switch occurs but that type of implementation
498	 * is more complex. So currently we will always save and
499	 * restore these registers on entry and exit of EL3.
500	 * These are not macros to ensure their invocation fits
501	 * within the 32 instructions per exception vector.
502	 * -----------------------------------------------------
503	 */
504func save_gp_registers
505	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
506	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
507	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
508	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
509	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
510	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
511	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
512	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
513	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
514	save_x18_to_x29_sp_el0
515	ret
516endfunc save_gp_registers
517
518func restore_gp_registers_eret
519	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
520	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
521
522restore_gp_registers_callee_eret:
523	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
524	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
525	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
526	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
527	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
528	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
529	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
530	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
531	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
532	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
533	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
534	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
535	ldp	x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
536	msr	sp_el0, x17
537	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
538	eret
539endfunc restore_gp_registers_eret
540