1/* 2 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <bl31/sync_handle.h> 14#include <common/runtime_svc.h> 15#include <context.h> 16#include <el3_common_macros.S> 17#include <lib/el3_runtime/cpu_data.h> 18#include <lib/smccc.h> 19 20 .globl runtime_exceptions 21 22 .globl sync_exception_sp_el0 23 .globl irq_sp_el0 24 .globl fiq_sp_el0 25 .globl serror_sp_el0 26 27 .globl sync_exception_sp_elx 28 .globl irq_sp_elx 29 .globl fiq_sp_elx 30 .globl serror_sp_elx 31 32 .globl sync_exception_aarch64 33 .globl irq_aarch64 34 .globl fiq_aarch64 35 .globl serror_aarch64 36 37 .globl sync_exception_aarch32 38 .globl irq_aarch32 39 .globl fiq_aarch32 40 .globl serror_aarch32 41 42 /* 43 * Save LR and make x30 available as most of the routines in vector entry 44 * need a free register 45 */ 46 .macro save_x30 47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 48 .endm 49 50 /* 51 * Macro that prepares entry to EL3 upon taking an exception. 52 * 53 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 54 * instruction. When an error is thus synchronized, the handling is 55 * delegated to platform EA handler. 56 * 57 * Without RAS_EXTENSION, this macro synchronizes pending errors using 58 * a DSB, unmasks Asynchronous External Aborts and saves X30 before 59 * setting the flag CTX_IS_IN_EL3. 60 */ 61 .macro check_and_unmask_ea 62#if RAS_EXTENSION 63 /* Synchronize pending External Aborts */ 64 esb 65 66 /* Unmask the SError interrupt */ 67 msr daifclr, #DAIF_ABT_BIT 68 69 /* Check for SErrors synchronized by the ESB instruction */ 70 mrs x30, DISR_EL1 71 tbz x30, #DISR_A_BIT, 1f 72 73 /* 74 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 75 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 76 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 77 * Also set the PSTATE to a known state. 78 */ 79 bl prepare_el3_entry 80 81 bl handle_lower_el_ea_esb 82 83 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ 84 bl restore_gp_pmcr_pauth_regs 851: 86#else 87 /* 88 * Note 1: The explicit DSB at the entry of various exception vectors 89 * for handling exceptions from lower ELs can inadvertently trigger an 90 * SError exception in EL3 due to pending asynchronous aborts in lower 91 * ELs. This will end up being handled by serror_sp_elx which will 92 * ultimately panic and die. 93 * The way to workaround is to update a flag to indicate if the exception 94 * truly came from EL3. This flag is allocated in the cpu_context 95 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3" 96 * This is not a bullet proof solution to the problem at hand because 97 * we assume the instructions following "isb" that help to update the 98 * flag execute without causing further exceptions. 99 */ 100 101 /* 102 * For SoCs which do not implement RAS, use DSB as a barrier to 103 * synchronize pending external aborts. 104 */ 105 dsb sy 106 107 /* Unmask the SError interrupt */ 108 msr daifclr, #DAIF_ABT_BIT 109 110 /* Use ISB for the above unmask operation to take effect immediately */ 111 isb 112 113 /* Refer Note 1. */ 114 mov x30, #1 115 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 116 dmb sy 117#endif 118 .endm 119 120 /* --------------------------------------------------------------------- 121 * This macro handles Synchronous exceptions. 122 * Only SMC exceptions are supported. 123 * --------------------------------------------------------------------- 124 */ 125 .macro handle_sync_exception 126#if ENABLE_RUNTIME_INSTRUMENTATION 127 /* 128 * Read the timestamp value and store it in per-cpu data. The value 129 * will be extracted from per-cpu data by the C level SMC handler and 130 * saved to the PMF timestamp region. 131 */ 132 mrs x30, cntpct_el0 133 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 134 mrs x29, tpidr_el3 135 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 136 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 137#endif 138 139 mrs x30, esr_el3 140 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 141 142 /* Handle SMC exceptions separately from other synchronous exceptions */ 143 cmp x30, #EC_AARCH32_SMC 144 b.eq smc_handler32 145 146 cmp x30, #EC_AARCH64_SMC 147 b.eq sync_handler64 148 149 cmp x30, #EC_AARCH64_SYS 150 b.eq sync_handler64 151 152 /* Synchronous exceptions other than the above are assumed to be EA */ 153 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 154 b handle_lower_el_sync_ea 155 .endm 156 157 158 /* --------------------------------------------------------------------- 159 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 160 * interrupts. 161 * --------------------------------------------------------------------- 162 */ 163 .macro handle_interrupt_exception label 164 165 /* 166 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 167 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 168 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 169 * Also set the PSTATE to a known state. 170 */ 171 bl prepare_el3_entry 172 173#if ENABLE_PAUTH 174 /* Load and program APIAKey firmware key */ 175 bl pauth_load_bl31_apiakey 176#endif 177 178 /* Save the EL3 system registers needed to return from this exception */ 179 mrs x0, spsr_el3 180 mrs x1, elr_el3 181 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 182 183 /* Switch to the runtime stack i.e. SP_EL0 */ 184 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 185 mov x20, sp 186 msr spsel, #MODE_SP_EL0 187 mov sp, x2 188 189 /* 190 * Find out whether this is a valid interrupt type. 191 * If the interrupt controller reports a spurious interrupt then return 192 * to where we came from. 193 */ 194 bl plat_ic_get_pending_interrupt_type 195 cmp x0, #INTR_TYPE_INVAL 196 b.eq interrupt_exit_\label 197 198 /* 199 * Get the registered handler for this interrupt type. 200 * A NULL return value could be 'cause of the following conditions: 201 * 202 * a. An interrupt of a type was routed correctly but a handler for its 203 * type was not registered. 204 * 205 * b. An interrupt of a type was not routed correctly so a handler for 206 * its type was not registered. 207 * 208 * c. An interrupt of a type was routed correctly to EL3, but was 209 * deasserted before its pending state could be read. Another 210 * interrupt of a different type pended at the same time and its 211 * type was reported as pending instead. However, a handler for this 212 * type was not registered. 213 * 214 * a. and b. can only happen due to a programming error. The 215 * occurrence of c. could be beyond the control of Trusted Firmware. 216 * It makes sense to return from this exception instead of reporting an 217 * error. 218 */ 219 bl get_interrupt_type_handler 220 cbz x0, interrupt_exit_\label 221 mov x21, x0 222 223 mov x0, #INTR_ID_UNAVAILABLE 224 225 /* Set the current security state in the 'flags' parameter */ 226 mrs x2, scr_el3 227 ubfx x1, x2, #0, #1 228 229 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 230 mov x2, x20 231 232 /* x3 will point to a cookie (not used now) */ 233 mov x3, xzr 234 235 /* Call the interrupt type handler */ 236 blr x21 237 238interrupt_exit_\label: 239 /* Return from exception, possibly in a different security state */ 240 b el3_exit 241 242 .endm 243 244 245vector_base runtime_exceptions 246 247 /* --------------------------------------------------------------------- 248 * Current EL with SP_EL0 : 0x0 - 0x200 249 * --------------------------------------------------------------------- 250 */ 251vector_entry sync_exception_sp_el0 252#ifdef MONITOR_TRAPS 253 stp x29, x30, [sp, #-16]! 254 255 mrs x30, esr_el3 256 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 257 258 /* Check for BRK */ 259 cmp x30, #EC_BRK 260 b.eq brk_handler 261 262 ldp x29, x30, [sp], #16 263#endif /* MONITOR_TRAPS */ 264 265 /* We don't expect any synchronous exceptions from EL3 */ 266 b report_unhandled_exception 267end_vector_entry sync_exception_sp_el0 268 269vector_entry irq_sp_el0 270 /* 271 * EL3 code is non-reentrant. Any asynchronous exception is a serious 272 * error. Loop infinitely. 273 */ 274 b report_unhandled_interrupt 275end_vector_entry irq_sp_el0 276 277 278vector_entry fiq_sp_el0 279 b report_unhandled_interrupt 280end_vector_entry fiq_sp_el0 281 282 283vector_entry serror_sp_el0 284 no_ret plat_handle_el3_ea 285end_vector_entry serror_sp_el0 286 287 /* --------------------------------------------------------------------- 288 * Current EL with SP_ELx: 0x200 - 0x400 289 * --------------------------------------------------------------------- 290 */ 291vector_entry sync_exception_sp_elx 292 /* 293 * This exception will trigger if anything went wrong during a previous 294 * exception entry or exit or while handling an earlier unexpected 295 * synchronous exception. There is a high probability that SP_EL3 is 296 * corrupted. 297 */ 298 b report_unhandled_exception 299end_vector_entry sync_exception_sp_elx 300 301vector_entry irq_sp_elx 302 b report_unhandled_interrupt 303end_vector_entry irq_sp_elx 304 305vector_entry fiq_sp_elx 306 b report_unhandled_interrupt 307end_vector_entry fiq_sp_elx 308 309vector_entry serror_sp_elx 310#if !RAS_EXTENSION 311 /* 312 * This will trigger if the exception was taken due to SError in EL3 or 313 * because of pending asynchronous external aborts from lower EL that got 314 * triggered due to explicit synchronization in EL3. Refer Note 1. 315 */ 316 /* Assumes SP_EL3 on entry */ 317 save_x30 318 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 319 cbnz x30, 1f 320 321 /* Handle asynchronous external abort from lower EL */ 322 b handle_lower_el_async_ea 3231: 324#endif 325 no_ret plat_handle_el3_ea 326end_vector_entry serror_sp_elx 327 328 /* --------------------------------------------------------------------- 329 * Lower EL using AArch64 : 0x400 - 0x600 330 * --------------------------------------------------------------------- 331 */ 332vector_entry sync_exception_aarch64 333 /* 334 * This exception vector will be the entry point for SMCs and traps 335 * that are unhandled at lower ELs most commonly. SP_EL3 should point 336 * to a valid cpu context where the general purpose and system register 337 * state can be saved. 338 */ 339 save_x30 340 apply_at_speculative_wa 341 check_and_unmask_ea 342 handle_sync_exception 343end_vector_entry sync_exception_aarch64 344 345vector_entry irq_aarch64 346 save_x30 347 apply_at_speculative_wa 348 check_and_unmask_ea 349 handle_interrupt_exception irq_aarch64 350end_vector_entry irq_aarch64 351 352vector_entry fiq_aarch64 353 save_x30 354 apply_at_speculative_wa 355 check_and_unmask_ea 356 handle_interrupt_exception fiq_aarch64 357end_vector_entry fiq_aarch64 358 359vector_entry serror_aarch64 360 save_x30 361 apply_at_speculative_wa 362#if RAS_EXTENSION 363 msr daifclr, #DAIF_ABT_BIT 364#else 365 check_and_unmask_ea 366#endif 367 b handle_lower_el_async_ea 368 369end_vector_entry serror_aarch64 370 371 /* --------------------------------------------------------------------- 372 * Lower EL using AArch32 : 0x600 - 0x800 373 * --------------------------------------------------------------------- 374 */ 375vector_entry sync_exception_aarch32 376 /* 377 * This exception vector will be the entry point for SMCs and traps 378 * that are unhandled at lower ELs most commonly. SP_EL3 should point 379 * to a valid cpu context where the general purpose and system register 380 * state can be saved. 381 */ 382 save_x30 383 apply_at_speculative_wa 384 check_and_unmask_ea 385 handle_sync_exception 386end_vector_entry sync_exception_aarch32 387 388vector_entry irq_aarch32 389 save_x30 390 apply_at_speculative_wa 391 check_and_unmask_ea 392 handle_interrupt_exception irq_aarch32 393end_vector_entry irq_aarch32 394 395vector_entry fiq_aarch32 396 save_x30 397 apply_at_speculative_wa 398 check_and_unmask_ea 399 handle_interrupt_exception fiq_aarch32 400end_vector_entry fiq_aarch32 401 402vector_entry serror_aarch32 403 save_x30 404 apply_at_speculative_wa 405#if RAS_EXTENSION 406 msr daifclr, #DAIF_ABT_BIT 407#else 408 check_and_unmask_ea 409#endif 410 b handle_lower_el_async_ea 411 412end_vector_entry serror_aarch32 413 414#ifdef MONITOR_TRAPS 415 .section .rodata.brk_string, "aS" 416brk_location: 417 .asciz "Error at instruction 0x" 418brk_message: 419 .asciz "Unexpected BRK instruction with value 0x" 420#endif /* MONITOR_TRAPS */ 421 422 /* --------------------------------------------------------------------- 423 * The following code handles secure monitor calls. 424 * Depending upon the execution state from where the SMC has been 425 * invoked, it frees some general purpose registers to perform the 426 * remaining tasks. They involve finding the runtime service handler 427 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 428 * before calling the handler. 429 * 430 * Note that x30 has been explicitly saved and can be used here 431 * --------------------------------------------------------------------- 432 */ 433func sync_exception_handler 434smc_handler32: 435 /* Check whether aarch32 issued an SMC64 */ 436 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 437 438sync_handler64: 439 /* NOTE: The code below must preserve x0-x4 */ 440 441 /* 442 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 443 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 444 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 445 * Also set the PSTATE to a known state. 446 */ 447 bl prepare_el3_entry 448 449#if ENABLE_PAUTH 450 /* Load and program APIAKey firmware key */ 451 bl pauth_load_bl31_apiakey 452#endif 453 454 /* 455 * Populate the parameters for the SMC handler. 456 * We already have x0-x4 in place. x5 will point to a cookie (not used 457 * now). x6 will point to the context structure (SP_EL3) and x7 will 458 * contain flags we need to pass to the handler. 459 */ 460 mov x5, xzr 461 mov x6, sp 462 463 /* 464 * Restore the saved C runtime stack value which will become the new 465 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 466 * structure prior to the last ERET from EL3. 467 */ 468 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 469 470 /* Switch to SP_EL0 */ 471 msr spsel, #MODE_SP_EL0 472 473 /* 474 * Save the SPSR_EL3 and ELR_EL3 in case there is a world 475 * switch during SMC handling. 476 * TODO: Revisit if all system registers can be saved later. 477 */ 478 mrs x16, spsr_el3 479 mrs x17, elr_el3 480 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 481 482 /* Load SCR_EL3 */ 483 mrs x18, scr_el3 484 485 /* check for system register traps */ 486 mrs x16, esr_el3 487 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH 488 cmp x17, #EC_AARCH64_SYS 489 b.eq sysreg_handler64 490 491 /* Clear flag register */ 492 mov x7, xzr 493 494#if ENABLE_RME 495 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ 496 ubfx x7, x18, #SCR_NSE_SHIFT, 1 497 498 /* 499 * Shift copied SCR_EL3.NSE bit by 5 to create space for 500 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to 501 * the SCR_EL3.NSE bit. 502 */ 503 lsl x7, x7, #5 504#endif /* ENABLE_RME */ 505 506 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 507 bfi x7, x18, #0, #1 508 509 /* 510 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID 511 * passed through x0. Copy the SVE hint bit to flags and mask the 512 * bit in smc_fid passed to the standard service dispatcher. 513 * A service/dispatcher can retrieve the SVE hint bit state from 514 * flags using the appropriate helper. 515 */ 516 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK 517 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) 518 519 mov sp, x12 520 521 /* Get the unique owning entity number */ 522 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 523 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 524 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 525 526 /* Load descriptor index from array of indices */ 527 adrp x14, rt_svc_descs_indices 528 add x14, x14, :lo12:rt_svc_descs_indices 529 ldrb w15, [x14, x16] 530 531 /* Any index greater than 127 is invalid. Check bit 7. */ 532 tbnz w15, 7, smc_unknown 533 534 /* 535 * Get the descriptor using the index 536 * x11 = (base + off), w15 = index 537 * 538 * handler = (base + off) + (index << log2(size)) 539 */ 540 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 541 lsl w10, w15, #RT_SVC_SIZE_LOG2 542 ldr x15, [x11, w10, uxtw] 543 544 /* 545 * Call the Secure Monitor Call handler and then drop directly into 546 * el3_exit() which will program any remaining architectural state 547 * prior to issuing the ERET to the desired lower EL. 548 */ 549#if DEBUG 550 cbz x15, rt_svc_fw_critical_error 551#endif 552 blr x15 553 554 b el3_exit 555 556sysreg_handler64: 557 mov x0, x16 /* ESR_EL3, containing syndrome information */ 558 mov x1, x6 /* lower EL's context */ 559 mov x19, x6 /* save context pointer for after the call */ 560 mov sp, x12 /* EL3 runtime stack, as loaded above */ 561 562 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ 563 bl handle_sysreg_trap 564 /* 565 * returns: 566 * -1: unhandled trap, panic 567 * 0: handled trap, return to the trapping instruction (repeating it) 568 * 1: handled trap, return to the next instruction 569 */ 570 571 tst w0, w0 572 b.mi elx_panic /* negative return value: panic */ 573 b.eq 1f /* zero: do not change ELR_EL3 */ 574 575 /* advance the PC to continue after the instruction */ 576 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 577 add x1, x1, #4 578 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 5791: 580 b el3_exit 581 582smc_unknown: 583 /* 584 * Unknown SMC call. Populate return value with SMC_UNK and call 585 * el3_exit() which will restore the remaining architectural state 586 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 587 * to the desired lower EL. 588 */ 589 mov x0, #SMC_UNK 590 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 591 b el3_exit 592 593smc_prohibited: 594 restore_ptw_el1_sys_regs 595 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 596 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 597 mov x0, #SMC_UNK 598 exception_return 599 600#if DEBUG 601rt_svc_fw_critical_error: 602 /* Switch to SP_ELx */ 603 msr spsel, #MODE_SP_ELX 604 no_ret report_unhandled_exception 605#endif 606endfunc sync_exception_handler 607 608 /* --------------------------------------------------------------------- 609 * The following code handles exceptions caused by BRK instructions. 610 * Following a BRK instruction, the only real valid cause of action is 611 * to print some information and panic, as the code that caused it is 612 * likely in an inconsistent internal state. 613 * 614 * This is initially intended to be used in conjunction with 615 * __builtin_trap. 616 * --------------------------------------------------------------------- 617 */ 618#ifdef MONITOR_TRAPS 619func brk_handler 620 /* Extract the ISS */ 621 mrs x10, esr_el3 622 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 623 624 /* Ensure the console is initialized */ 625 bl plat_crash_console_init 626 627 adr x4, brk_location 628 bl asm_print_str 629 mrs x4, elr_el3 630 bl asm_print_hex 631 bl asm_print_newline 632 633 adr x4, brk_message 634 bl asm_print_str 635 mov x4, x10 636 mov x5, #28 637 bl asm_print_hex_bits 638 bl asm_print_newline 639 640 no_ret plat_panic_handler 641endfunc brk_handler 642#endif /* MONITOR_TRAPS */ 643