xref: /rk3399_ARM-atf/bl31/aarch64/runtime_exceptions.S (revision 649dbf6f3666fa4ec8bad318d01b946fb89063e0) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <context.h>
34#include <interrupt_mgmt.h>
35#include <platform_def.h>
36#include <runtime_svc.h>
37
38	.globl	runtime_exceptions
39	.globl	el3_exit
40
41	/* -----------------------------------------------------
42	 * Handle SMC exceptions separately from other sync.
43	 * exceptions.
44	 * -----------------------------------------------------
45	 */
46	.macro	handle_sync_exception
47	/* Enable the SError interrupt */
48	msr	daifclr, #DAIF_ABT_BIT
49
50	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
51	mrs	x30, esr_el3
52	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
53
54	cmp	x30, #EC_AARCH32_SMC
55	b.eq	smc_handler32
56
57	cmp	x30, #EC_AARCH64_SMC
58	b.eq	smc_handler64
59
60	/* -----------------------------------------------------
61	 * The following code handles any synchronous exception
62	 * that is not an SMC.
63	 * -----------------------------------------------------
64	 */
65
66	bl	report_unhandled_exception
67	.endm
68
69
70	/* -----------------------------------------------------
71	 * This macro handles FIQ or IRQ interrupts i.e. EL3,
72	 * S-EL1 and NS interrupts.
73	 * -----------------------------------------------------
74	 */
75	.macro	handle_interrupt_exception label
76	/* Enable the SError interrupt */
77	msr	daifclr, #DAIF_ABT_BIT
78
79	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
80	bl	save_gp_registers
81
82	/*
83	 * Save the EL3 system registers needed to return from
84	 * this exception.
85	 */
86	mrs	x0, spsr_el3
87	mrs	x1, elr_el3
88	stp	x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
89
90	/* Switch to the runtime stack i.e. SP_EL0 */
91	ldr	x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
92	mov	x20, sp
93	msr	spsel, #0
94	mov	sp, x2
95
96	/*
97	 * Find out whether this is a valid interrupt type. If the
98	 * interrupt controller reports a spurious interrupt then
99	 * return to where we came from.
100	 */
101	bl	plat_ic_get_pending_interrupt_type
102	cmp	x0, #INTR_TYPE_INVAL
103	b.eq	interrupt_exit_\label
104
105	/*
106	 * Get the registered handler for this interrupt type. A
107	 * NULL return value could be 'cause of the following
108	 * conditions:
109	 *
110	 * a. An interrupt of a type was routed correctly but a
111	 *    handler for its type was not registered.
112	 *
113	 * b. An interrupt of a type was not routed correctly so
114	 *    a handler for its type was not registered.
115	 *
116	 * c. An interrupt of a type was routed correctly to EL3,
117	 *    but was deasserted before its pending state could
118	 *    be read. Another interrupt of a different type pended
119	 *    at the same time and its type was reported as pending
120	 *    instead. However, a handler for this type was not
121	 *    registered.
122	 *
123	 * a. and b. can only happen due to a programming error.
124	 * The occurrence of c. could be beyond the control of
125	 * Trusted Firmware. It makes sense to return from this
126	 * exception instead of reporting an error.
127	 */
128	bl	get_interrupt_type_handler
129	cbz	x0, interrupt_exit_\label
130	mov	x21, x0
131
132	mov	x0, #INTR_ID_UNAVAILABLE
133
134	/* Set the current security state in the 'flags' parameter */
135	mrs	x2, scr_el3
136	ubfx	x1, x2, #0, #1
137
138	/* Restore the reference to the 'handle' i.e. SP_EL3 */
139	mov	x2, x20
140
141	/*  x3 will point to a cookie (not used now) */
142	mov	x3, xzr
143
144	/* Call the interrupt type handler */
145	blr	x21
146
147interrupt_exit_\label:
148	/* Return from exception, possibly in a different security state */
149	b	el3_exit
150
151	.endm
152
153
154	.macro save_x18_to_x29_sp_el0
155	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
156	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
157	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
158	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
159	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
160	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
161	mrs	x18, sp_el0
162	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
163	.endm
164
165	.section	.vectors, "ax"; .align 11
166	.align	7
167runtime_exceptions:
168	/* -----------------------------------------------------
169	 * Current EL with _sp_el0 : 0x0 - 0x200
170	 * -----------------------------------------------------
171	 */
172sync_exception_sp_el0:
173	/* -----------------------------------------------------
174	 * We don't expect any synchronous exceptions from EL3
175	 * -----------------------------------------------------
176	 */
177	bl	report_unhandled_exception
178	check_vector_size sync_exception_sp_el0
179
180	.align	7
181	/* -----------------------------------------------------
182	 * EL3 code is non-reentrant. Any asynchronous exception
183	 * is a serious error. Loop infinitely.
184	 * -----------------------------------------------------
185	 */
186irq_sp_el0:
187	bl	report_unhandled_interrupt
188	check_vector_size irq_sp_el0
189
190	.align	7
191fiq_sp_el0:
192	bl	report_unhandled_interrupt
193	check_vector_size fiq_sp_el0
194
195	.align	7
196serror_sp_el0:
197	bl	report_unhandled_exception
198	check_vector_size serror_sp_el0
199
200	/* -----------------------------------------------------
201	 * Current EL with SPx: 0x200 - 0x400
202	 * -----------------------------------------------------
203	 */
204	.align	7
205sync_exception_sp_elx:
206	/* -----------------------------------------------------
207	 * This exception will trigger if anything went wrong
208	 * during a previous exception entry or exit or while
209	 * handling an earlier unexpected synchronous exception.
210	 * There is a high probability that SP_EL3 is corrupted.
211	 * -----------------------------------------------------
212	 */
213	bl	report_unhandled_exception
214	check_vector_size sync_exception_sp_elx
215
216	.align	7
217irq_sp_elx:
218	bl	report_unhandled_interrupt
219	check_vector_size irq_sp_elx
220
221	.align	7
222fiq_sp_elx:
223	bl	report_unhandled_interrupt
224	check_vector_size fiq_sp_elx
225
226	.align	7
227serror_sp_elx:
228	bl	report_unhandled_exception
229	check_vector_size serror_sp_elx
230
231	/* -----------------------------------------------------
232	 * Lower EL using AArch64 : 0x400 - 0x600
233	 * -----------------------------------------------------
234	 */
235	.align	7
236sync_exception_aarch64:
237	/* -----------------------------------------------------
238	 * This exception vector will be the entry point for
239	 * SMCs and traps that are unhandled at lower ELs most
240	 * commonly. SP_EL3 should point to a valid cpu context
241	 * where the general purpose and system register state
242	 * can be saved.
243	 * -----------------------------------------------------
244	 */
245	handle_sync_exception
246	check_vector_size sync_exception_aarch64
247
248	.align	7
249	/* -----------------------------------------------------
250	 * Asynchronous exceptions from lower ELs are not
251	 * currently supported. Report their occurrence.
252	 * -----------------------------------------------------
253	 */
254irq_aarch64:
255	handle_interrupt_exception irq_aarch64
256	check_vector_size irq_aarch64
257
258	.align	7
259fiq_aarch64:
260	handle_interrupt_exception fiq_aarch64
261	check_vector_size fiq_aarch64
262
263	.align	7
264serror_aarch64:
265	bl	report_unhandled_exception
266	check_vector_size serror_aarch64
267
268	/* -----------------------------------------------------
269	 * Lower EL using AArch32 : 0x600 - 0x800
270	 * -----------------------------------------------------
271	 */
272	.align	7
273sync_exception_aarch32:
274	/* -----------------------------------------------------
275	 * This exception vector will be the entry point for
276	 * SMCs and traps that are unhandled at lower ELs most
277	 * commonly. SP_EL3 should point to a valid cpu context
278	 * where the general purpose and system register state
279	 * can be saved.
280	 * -----------------------------------------------------
281	 */
282	handle_sync_exception
283	check_vector_size sync_exception_aarch32
284
285	.align	7
286	/* -----------------------------------------------------
287	 * Asynchronous exceptions from lower ELs are not
288	 * currently supported. Report their occurrence.
289	 * -----------------------------------------------------
290	 */
291irq_aarch32:
292	handle_interrupt_exception irq_aarch32
293	check_vector_size irq_aarch32
294
295	.align	7
296fiq_aarch32:
297	handle_interrupt_exception fiq_aarch32
298	check_vector_size fiq_aarch32
299
300	.align	7
301serror_aarch32:
302	bl	report_unhandled_exception
303	check_vector_size serror_aarch32
304
305	.align	7
306
307	/* -----------------------------------------------------
308	 * The following code handles secure monitor calls.
309	 * Depending upon the execution state from where the SMC
310	 * has been invoked, it frees some general purpose
311	 * registers to perform the remaining tasks. They
312	 * involve finding the runtime service handler that is
313	 * the target of the SMC & switching to runtime stacks
314	 * (SP_EL0) before calling the handler.
315	 *
316	 * Note that x30 has been explicitly saved and can be
317	 * used here
318	 * -----------------------------------------------------
319	 */
320func smc_handler
321smc_handler32:
322	/* Check whether aarch32 issued an SMC64 */
323	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
324
325	/* -----------------------------------------------------
326	 * Since we're are coming from aarch32, x8-x18 need to
327	 * be saved as per SMC32 calling convention. If a lower
328	 * EL in aarch64 is making an SMC32 call then it must
329	 * have saved x8-x17 already therein.
330	 * -----------------------------------------------------
331	 */
332	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
333	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
334	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
335	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
336	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
337
338	/* x4-x7, x18, sp_el0 are saved below */
339
340smc_handler64:
341	/* -----------------------------------------------------
342	 * Populate the parameters for the SMC handler. We
343	 * already have x0-x4 in place. x5 will point to a
344	 * cookie (not used now). x6 will point to the context
345	 * structure (SP_EL3) and x7 will contain flags we need
346	 * to pass to the handler Hence save x5-x7. Note that x4
347	 * only needs to be preserved for AArch32 callers but we
348	 * do it for AArch64 callers as well for convenience
349	 * -----------------------------------------------------
350	 */
351	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
352	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
353
354	/* Save rest of the gpregs and sp_el0*/
355	save_x18_to_x29_sp_el0
356
357	mov	x5, xzr
358	mov	x6, sp
359
360	/* Get the unique owning entity number */
361	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
362	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
363	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
364
365	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
366
367	/* Load descriptor index from array of indices */
368	adr	x14, rt_svc_descs_indices
369	ldrb	w15, [x14, x16]
370
371	/* -----------------------------------------------------
372	 * Restore the saved C runtime stack value which will
373	 * become the new SP_EL0 i.e. EL3 runtime stack. It was
374	 * saved in the 'cpu_context' structure prior to the last
375	 * ERET from EL3.
376	 * -----------------------------------------------------
377	 */
378	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
379
380	/*
381	 * Any index greater than 127 is invalid. Check bit 7 for
382	 * a valid index
383	 */
384	tbnz	w15, 7, smc_unknown
385
386	/* Switch to SP_EL0 */
387	msr	spsel, #0
388
389	/* -----------------------------------------------------
390	 * Get the descriptor using the index
391	 * x11 = (base + off), x15 = index
392	 *
393	 * handler = (base + off) + (index << log2(size))
394	 * -----------------------------------------------------
395	 */
396	lsl	w10, w15, #RT_SVC_SIZE_LOG2
397	ldr	x15, [x11, w10, uxtw]
398
399	/* -----------------------------------------------------
400	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
401	 * is a world switch during SMC handling.
402	 * TODO: Revisit if all system registers can be saved
403	 * later.
404	 * -----------------------------------------------------
405	 */
406	mrs	x16, spsr_el3
407	mrs	x17, elr_el3
408	mrs	x18, scr_el3
409	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
410	str	x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
411
412	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
413	bfi	x7, x18, #0, #1
414
415	mov	sp, x12
416
417	/* -----------------------------------------------------
418	 * Call the Secure Monitor Call handler and then drop
419	 * directly into el3_exit() which will program any
420	 * remaining architectural state prior to issuing the
421	 * ERET to the desired lower EL.
422	 * -----------------------------------------------------
423	 */
424#if DEBUG
425	cbz	x15, rt_svc_fw_critical_error
426#endif
427	blr	x15
428
429	/* -----------------------------------------------------
430	 * This routine assumes that the SP_EL3 is pointing to
431	 * a valid context structure from where the gp regs and
432	 * other special registers can be retrieved.
433	 *
434	 * Keep it in the same section as smc_handler as this
435	 * function uses a fall-through to el3_exit
436	 * -----------------------------------------------------
437	 */
438el3_exit: ; .type el3_exit, %function
439	/* -----------------------------------------------------
440	 * Save the current SP_EL0 i.e. the EL3 runtime stack
441	 * which will be used for handling the next SMC. Then
442	 * switch to SP_EL3
443	 * -----------------------------------------------------
444	 */
445	mov	x17, sp
446	msr	spsel, #1
447	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
448
449	/* -----------------------------------------------------
450	 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
451	 * -----------------------------------------------------
452	 */
453	ldr	x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
454	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
455	msr	scr_el3, x18
456	msr	spsr_el3, x16
457	msr	elr_el3, x17
458
459	/* Restore saved general purpose registers and return */
460	b	restore_gp_registers_eret
461
462smc_unknown:
463	/*
464	 * Here we restore x4-x18 regardless of where we came from. AArch32
465	 * callers will find the registers contents unchanged, but AArch64
466	 * callers will find the registers modified (with stale earlier NS
467	 * content). Either way, we aren't leaking any secure information
468	 * through them
469	 */
470	mov	w0, #SMC_UNK
471	b	restore_gp_registers_callee_eret
472
473smc_prohibited:
474	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
475	mov	w0, #SMC_UNK
476	eret
477
478rt_svc_fw_critical_error:
479	msr	spsel, #1 /* Switch to SP_ELx */
480	bl	report_unhandled_exception
481endfunc smc_handler
482
483	/* -----------------------------------------------------
484	 * The following functions are used to saved and restore
485	 * all the general pupose registers. Ideally we would
486	 * only save and restore the callee saved registers when
487	 * a world switch occurs but that type of implementation
488	 * is more complex. So currently we will always save and
489	 * restore these registers on entry and exit of EL3.
490	 * These are not macros to ensure their invocation fits
491	 * within the 32 instructions per exception vector.
492	 * -----------------------------------------------------
493	 */
494func save_gp_registers
495	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
496	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
497	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
498	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
499	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
500	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
501	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
502	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
503	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
504	save_x18_to_x29_sp_el0
505	ret
506endfunc save_gp_registers
507
508func restore_gp_registers_eret
509	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
510	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
511
512restore_gp_registers_callee_eret:
513	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
514	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
515	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
516	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
517	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
518	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
519	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
520	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
521	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
522	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
523	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
524	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
525	ldp	x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
526	msr	sp_el0, x17
527	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
528	eret
529endfunc restore_gp_registers_eret
530