xref: /rk3399_ARM-atf/bl31/aarch64/runtime_exceptions.S (revision 539a7b383d52493a94df4f5da8f74aa102429fa0) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <context.h>
34#include <interrupt_mgmt.h>
35#include <platform_def.h>
36#include <runtime_svc.h>
37
38	.globl	runtime_exceptions
39	.globl	el3_exit
40
41	/* -----------------------------------------------------
42	 * Handle SMC exceptions seperately from other sync.
43	 * exceptions.
44	 * -----------------------------------------------------
45	 */
46	.macro	handle_sync_exception
47	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
48	mrs	x30, esr_el3
49	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
50
51	cmp	x30, #EC_AARCH32_SMC
52	b.eq	smc_handler32
53
54	cmp	x30, #EC_AARCH64_SMC
55	b.eq	smc_handler64
56
57	/* -----------------------------------------------------
58	 * The following code handles any synchronous exception
59	 * that is not an SMC.
60	 * -----------------------------------------------------
61	 */
62
63	bl	dump_state_and_die
64	.endm
65
66
67	/* -----------------------------------------------------
68	 * This macro handles FIQ or IRQ interrupts i.e. EL3,
69	 * S-EL1 and NS interrupts.
70	 * -----------------------------------------------------
71	 */
72	.macro	handle_interrupt_exception label
73	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
74	bl	save_gp_registers
75
76	/* Switch to the runtime stack i.e. SP_EL0 */
77	ldr	x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
78	mov	x20, sp
79	msr	spsel, #0
80	mov	sp, x2
81
82	/*
83	 * Find out whether this is a valid interrupt type. If the
84	 * interrupt controller reports a spurious interrupt then
85	 * return to where we came from.
86	 */
87	bl	plat_ic_get_pending_interrupt_type
88	cmp	x0, #INTR_TYPE_INVAL
89	b.eq	interrupt_exit_\label
90
91	/*
92	 * Get the registered handler for this interrupt type. A
93	 * NULL return value implies that an interrupt was generated
94	 * for which there is no handler registered or the interrupt
95	 * was routed incorrectly. This is a problem of the framework
96	 * so report it as an error.
97	 */
98	bl	get_interrupt_type_handler
99	cbz	x0, interrupt_error_\label
100	mov	x21, x0
101
102	mov	x0, #INTR_ID_UNAVAILABLE
103#if IMF_READ_INTERRUPT_ID
104	/*
105	 * Read the id of the highest priority pending interrupt. If
106	 * no interrupt is asserted then return to where we came from.
107	 */
108	mov	x19,  #INTR_ID_UNAVAILABLE
109	bl	plat_ic_get_pending_interrupt_id
110	cmp	x19, x0
111	b.eq	interrupt_exit_\label
112#endif
113
114	/*
115	 * Save the EL3 system registers needed to return from
116	 * this exception.
117	 */
118	mrs	x3, spsr_el3
119	mrs	x4, elr_el3
120	stp	x3, x4, [x20, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
121
122	/* Set the current security state in the 'flags' parameter */
123	mrs	x2, scr_el3
124	ubfx	x1, x2, #0, #1
125
126	/* Restore the reference to the 'handle' i.e. SP_EL3 */
127	mov	x2, x20
128
129	/*  x3 will point to a cookie (not used now) */
130	mov	x3, xzr
131
132	/* Call the interrupt type handler */
133	blr	x21
134
135interrupt_exit_\label:
136	/* Return from exception, possibly in a different security state */
137	b	el3_exit
138
139	/*
140	 * This label signifies a problem with the interrupt management
141	 * framework where it is not safe to go back to the instruction
142	 * where the interrupt was generated.
143	 */
144interrupt_error_\label:
145	bl	dump_intr_state_and_die
146	.endm
147
148
149	.macro save_x18_to_x29_sp_el0
150	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
151	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
152	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
153	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
154	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
155	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
156	mrs	x18, sp_el0
157	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
158	.endm
159
160	.section	.vectors, "ax"; .align 11
161
162	.align	7
163runtime_exceptions:
164	/* -----------------------------------------------------
165	 * Current EL with _sp_el0 : 0x0 - 0x180
166	 * -----------------------------------------------------
167	 */
168sync_exception_sp_el0:
169	/* -----------------------------------------------------
170	 * We don't expect any synchronous exceptions from EL3
171	 * -----------------------------------------------------
172	 */
173	bl	dump_state_and_die
174	check_vector_size sync_exception_sp_el0
175
176	.align	7
177	/* -----------------------------------------------------
178	 * EL3 code is non-reentrant. Any asynchronous exception
179	 * is a serious error. Loop infinitely.
180	 * -----------------------------------------------------
181	 */
182irq_sp_el0:
183	bl	dump_intr_state_and_die
184	check_vector_size irq_sp_el0
185
186	.align	7
187fiq_sp_el0:
188	bl	dump_intr_state_and_die
189	check_vector_size fiq_sp_el0
190
191	.align	7
192serror_sp_el0:
193	bl	dump_state_and_die
194	check_vector_size serror_sp_el0
195
196	/* -----------------------------------------------------
197	 * Current EL with SPx: 0x200 - 0x380
198	 * -----------------------------------------------------
199	 */
200	.align	7
201sync_exception_sp_elx:
202	/* -----------------------------------------------------
203	 * This exception will trigger if anything went wrong
204	 * during a previous exception entry or exit or while
205	 * handling an earlier unexpected synchronous exception.
206	 * There is a high probability that SP_EL3 is corrupted.
207	 * -----------------------------------------------------
208	 */
209	bl	dump_state_and_die
210	check_vector_size sync_exception_sp_elx
211
212	.align	7
213irq_sp_elx:
214	bl	dump_intr_state_and_die
215	check_vector_size irq_sp_elx
216
217	.align	7
218fiq_sp_elx:
219	bl	dump_intr_state_and_die
220	check_vector_size fiq_sp_elx
221
222	.align	7
223serror_sp_elx:
224	bl	dump_state_and_die
225	check_vector_size serror_sp_elx
226
227	/* -----------------------------------------------------
228	 * Lower EL using AArch64 : 0x400 - 0x580
229	 * -----------------------------------------------------
230	 */
231	.align	7
232sync_exception_aarch64:
233	/* -----------------------------------------------------
234	 * This exception vector will be the entry point for
235	 * SMCs and traps that are unhandled at lower ELs most
236	 * commonly. SP_EL3 should point to a valid cpu context
237	 * where the general purpose and system register state
238	 * can be saved.
239	 * -----------------------------------------------------
240	 */
241	handle_sync_exception
242	check_vector_size sync_exception_aarch64
243
244	.align	7
245	/* -----------------------------------------------------
246	 * Asynchronous exceptions from lower ELs are not
247	 * currently supported. Report their occurrence.
248	 * -----------------------------------------------------
249	 */
250irq_aarch64:
251	handle_interrupt_exception irq_aarch64
252	check_vector_size irq_aarch64
253
254	.align	7
255fiq_aarch64:
256	handle_interrupt_exception fiq_aarch64
257	check_vector_size fiq_aarch64
258
259	.align	7
260serror_aarch64:
261	bl	dump_state_and_die
262	check_vector_size serror_aarch64
263
264	/* -----------------------------------------------------
265	 * Lower EL using AArch32 : 0x600 - 0x780
266	 * -----------------------------------------------------
267	 */
268	.align	7
269sync_exception_aarch32:
270	/* -----------------------------------------------------
271	 * This exception vector will be the entry point for
272	 * SMCs and traps that are unhandled at lower ELs most
273	 * commonly. SP_EL3 should point to a valid cpu context
274	 * where the general purpose and system register state
275	 * can be saved.
276	 * -----------------------------------------------------
277	 */
278	handle_sync_exception
279	check_vector_size sync_exception_aarch32
280
281	.align	7
282	/* -----------------------------------------------------
283	 * Asynchronous exceptions from lower ELs are not
284	 * currently supported. Report their occurrence.
285	 * -----------------------------------------------------
286	 */
287irq_aarch32:
288	handle_interrupt_exception irq_aarch32
289	check_vector_size irq_aarch32
290
291	.align	7
292fiq_aarch32:
293	handle_interrupt_exception fiq_aarch32
294	check_vector_size fiq_aarch32
295
296	.align	7
297serror_aarch32:
298	bl	dump_state_and_die
299	check_vector_size serror_aarch32
300
301	.align	7
302
303	/* -----------------------------------------------------
304	 * The following code handles secure monitor calls.
305	 * Depending upon the execution state from where the SMC
306	 * has been invoked, it frees some general purpose
307	 * registers to perform the remaining tasks. They
308	 * involve finding the runtime service handler that is
309	 * the target of the SMC & switching to runtime stacks
310	 * (SP_EL0) before calling the handler.
311	 *
312	 * Note that x30 has been explicitly saved and can be
313	 * used here
314	 * -----------------------------------------------------
315	 */
316func smc_handler
317smc_handler32:
318	/* Check whether aarch32 issued an SMC64 */
319	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
320
321	/* -----------------------------------------------------
322	 * Since we're are coming from aarch32, x8-x18 need to
323	 * be saved as per SMC32 calling convention. If a lower
324	 * EL in aarch64 is making an SMC32 call then it must
325	 * have saved x8-x17 already therein.
326	 * -----------------------------------------------------
327	 */
328	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
329	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
330	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
331	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
332	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
333
334	/* x4-x7, x18, sp_el0 are saved below */
335
336smc_handler64:
337	/* -----------------------------------------------------
338	 * Populate the parameters for the SMC handler. We
339	 * already have x0-x4 in place. x5 will point to a
340	 * cookie (not used now). x6 will point to the context
341	 * structure (SP_EL3) and x7 will contain flags we need
342	 * to pass to the handler Hence save x5-x7. Note that x4
343	 * only needs to be preserved for AArch32 callers but we
344	 * do it for AArch64 callers as well for convenience
345	 * -----------------------------------------------------
346	 */
347	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
348	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
349
350	/* Save rest of the gpregs and sp_el0*/
351	save_x18_to_x29_sp_el0
352
353	mov	x5, xzr
354	mov	x6, sp
355
356	/* Get the unique owning entity number */
357	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
358	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
359	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
360
361	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
362
363	/* Load descriptor index from array of indices */
364	adr	x14, rt_svc_descs_indices
365	ldrb	w15, [x14, x16]
366
367	/* -----------------------------------------------------
368	 * Restore the saved C runtime stack value which will
369	 * become the new SP_EL0 i.e. EL3 runtime stack. It was
370	 * saved in the 'cpu_context' structure prior to the last
371	 * ERET from EL3.
372	 * -----------------------------------------------------
373	 */
374	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
375
376	/*
377	 * Any index greater than 127 is invalid. Check bit 7 for
378	 * a valid index
379	 */
380	tbnz	w15, 7, smc_unknown
381
382	/* Switch to SP_EL0 */
383	msr	spsel, #0
384
385	/* -----------------------------------------------------
386	 * Get the descriptor using the index
387	 * x11 = (base + off), x15 = index
388	 *
389	 * handler = (base + off) + (index << log2(size))
390	 * -----------------------------------------------------
391	 */
392	lsl	w10, w15, #RT_SVC_SIZE_LOG2
393	ldr	x15, [x11, w10, uxtw]
394
395	/* -----------------------------------------------------
396	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
397	 * is a world switch during SMC handling.
398	 * TODO: Revisit if all system registers can be saved
399	 * later.
400	 * -----------------------------------------------------
401	 */
402	mrs	x16, spsr_el3
403	mrs	x17, elr_el3
404	mrs	x18, scr_el3
405	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
406	str	x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
407
408	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
409	bfi	x7, x18, #0, #1
410
411	mov	sp, x12
412
413	/* -----------------------------------------------------
414	 * Call the Secure Monitor Call handler and then drop
415	 * directly into el3_exit() which will program any
416	 * remaining architectural state prior to issuing the
417	 * ERET to the desired lower EL.
418	 * -----------------------------------------------------
419	 */
420#if DEBUG
421	cbz	x15, rt_svc_fw_critical_error
422#endif
423	blr	x15
424
425	/* -----------------------------------------------------
426	 * This routine assumes that the SP_EL3 is pointing to
427	 * a valid context structure from where the gp regs and
428	 * other special registers can be retrieved.
429	 *
430	 * Keep it in the same section as smc_handler as this
431	 * function uses a fall-through to el3_exit
432	 * -----------------------------------------------------
433	 */
434el3_exit: ; .type el3_exit, %function
435	/* -----------------------------------------------------
436	 * Save the current SP_EL0 i.e. the EL3 runtime stack
437	 * which will be used for handling the next SMC. Then
438	 * switch to SP_EL3
439	 * -----------------------------------------------------
440	 */
441	mov	x17, sp
442	msr	spsel, #1
443	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
444
445	/* -----------------------------------------------------
446	 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
447	 * -----------------------------------------------------
448	 */
449	ldr	x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
450	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
451	msr	scr_el3, x18
452	msr	spsr_el3, x16
453	msr	elr_el3, x17
454
455	/* Restore saved general purpose registers and return */
456	b	restore_gp_registers_eret
457
458smc_unknown:
459	/*
460	 * Here we restore x4-x18 regardless of where we came from. AArch32
461	 * callers will find the registers contents unchanged, but AArch64
462	 * callers will find the registers modified (with stale earlier NS
463	 * content). Either way, we aren't leaking any secure information
464	 * through them
465	 */
466	mov	w0, #SMC_UNK
467	b	restore_gp_registers_callee_eret
468
469smc_prohibited:
470	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
471	mov	w0, #SMC_UNK
472	eret
473
474rt_svc_fw_critical_error:
475	msr	spsel, #1 /* Switch to SP_ELx */
476	bl	dump_state_and_die
477
478	/* -----------------------------------------------------
479	 * The following functions are used to saved and restore
480	 * all the general pupose registers. Ideally we would
481	 * only save and restore the callee saved registers when
482	 * a world switch occurs but that type of implementation
483	 * is more complex. So currently we will always save and
484	 * restore these registers on entry and exit of EL3.
485	 * These are not macros to ensure their invocation fits
486	 * within the 32 instructions per exception vector.
487	 * -----------------------------------------------------
488	 */
489func save_gp_registers
490	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
491	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
492	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
493	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
494	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
495	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
496	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
497	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
498	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
499	save_x18_to_x29_sp_el0
500	ret
501
502func restore_gp_registers_eret
503	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
504	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
505
506restore_gp_registers_callee_eret:
507	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
508	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
509	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
510	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
511	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
512	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
513	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
514	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
515	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
516	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
517	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
518	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
519	ldp	x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
520	msr	sp_el0, x17
521	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
522	eret
523