1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <context.h> 34#include <cpu_data.h> 35#include <interrupt_mgmt.h> 36#include <platform_def.h> 37#include <runtime_svc.h> 38 39 .globl runtime_exceptions 40 41 /* --------------------------------------------------------------------- 42 * This macro handles Synchronous exceptions. 43 * Only SMC exceptions are supported. 44 * --------------------------------------------------------------------- 45 */ 46 .macro handle_sync_exception 47 /* Enable the SError interrupt */ 48 msr daifclr, #DAIF_ABT_BIT 49 50 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 51 52#if ENABLE_RUNTIME_INSTRUMENTATION 53 /* 54 * Read the timestamp value and store it in per-cpu data. The value 55 * will be extracted from per-cpu data by the C level SMC handler and 56 * saved to the PMF timestamp region. 57 */ 58 mrs x30, cntpct_el0 59 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 60 mrs x29, tpidr_el3 61 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 62 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 63#endif 64 65 mrs x30, esr_el3 66 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 67 68 /* Handle SMC exceptions separately from other synchronous exceptions */ 69 cmp x30, #EC_AARCH32_SMC 70 b.eq smc_handler32 71 72 cmp x30, #EC_AARCH64_SMC 73 b.eq smc_handler64 74 75 /* Other kinds of synchronous exceptions are not handled */ 76 no_ret report_unhandled_exception 77 .endm 78 79 80 /* --------------------------------------------------------------------- 81 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 82 * interrupts. 83 * --------------------------------------------------------------------- 84 */ 85 .macro handle_interrupt_exception label 86 /* Enable the SError interrupt */ 87 msr daifclr, #DAIF_ABT_BIT 88 89 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 90 bl save_gp_registers 91 92 /* Save the EL3 system registers needed to return from this exception */ 93 mrs x0, spsr_el3 94 mrs x1, elr_el3 95 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 96 97 /* Switch to the runtime stack i.e. SP_EL0 */ 98 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 99 mov x20, sp 100 msr spsel, #0 101 mov sp, x2 102 103 /* 104 * Find out whether this is a valid interrupt type. 105 * If the interrupt controller reports a spurious interrupt then return 106 * to where we came from. 107 */ 108 bl plat_ic_get_pending_interrupt_type 109 cmp x0, #INTR_TYPE_INVAL 110 b.eq interrupt_exit_\label 111 112 /* 113 * Get the registered handler for this interrupt type. 114 * A NULL return value could be 'cause of the following conditions: 115 * 116 * a. An interrupt of a type was routed correctly but a handler for its 117 * type was not registered. 118 * 119 * b. An interrupt of a type was not routed correctly so a handler for 120 * its type was not registered. 121 * 122 * c. An interrupt of a type was routed correctly to EL3, but was 123 * deasserted before its pending state could be read. Another 124 * interrupt of a different type pended at the same time and its 125 * type was reported as pending instead. However, a handler for this 126 * type was not registered. 127 * 128 * a. and b. can only happen due to a programming error. The 129 * occurrence of c. could be beyond the control of Trusted Firmware. 130 * It makes sense to return from this exception instead of reporting an 131 * error. 132 */ 133 bl get_interrupt_type_handler 134 cbz x0, interrupt_exit_\label 135 mov x21, x0 136 137 mov x0, #INTR_ID_UNAVAILABLE 138 139 /* Set the current security state in the 'flags' parameter */ 140 mrs x2, scr_el3 141 ubfx x1, x2, #0, #1 142 143 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 144 mov x2, x20 145 146 /* x3 will point to a cookie (not used now) */ 147 mov x3, xzr 148 149 /* Call the interrupt type handler */ 150 blr x21 151 152interrupt_exit_\label: 153 /* Return from exception, possibly in a different security state */ 154 b el3_exit 155 156 .endm 157 158 159 .macro save_x18_to_x29_sp_el0 160 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 161 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 162 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 163 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 164 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 165 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 166 mrs x18, sp_el0 167 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 168 .endm 169 170 171vector_base runtime_exceptions 172 173 /* --------------------------------------------------------------------- 174 * Current EL with SP_EL0 : 0x0 - 0x200 175 * --------------------------------------------------------------------- 176 */ 177vector_entry sync_exception_sp_el0 178 /* We don't expect any synchronous exceptions from EL3 */ 179 no_ret report_unhandled_exception 180 check_vector_size sync_exception_sp_el0 181 182vector_entry irq_sp_el0 183 /* 184 * EL3 code is non-reentrant. Any asynchronous exception is a serious 185 * error. Loop infinitely. 186 */ 187 no_ret report_unhandled_interrupt 188 check_vector_size irq_sp_el0 189 190 191vector_entry fiq_sp_el0 192 no_ret report_unhandled_interrupt 193 check_vector_size fiq_sp_el0 194 195 196vector_entry serror_sp_el0 197 no_ret report_unhandled_exception 198 check_vector_size serror_sp_el0 199 200 /* --------------------------------------------------------------------- 201 * Current EL with SP_ELx: 0x200 - 0x400 202 * --------------------------------------------------------------------- 203 */ 204vector_entry sync_exception_sp_elx 205 /* 206 * This exception will trigger if anything went wrong during a previous 207 * exception entry or exit or while handling an earlier unexpected 208 * synchronous exception. There is a high probability that SP_EL3 is 209 * corrupted. 210 */ 211 no_ret report_unhandled_exception 212 check_vector_size sync_exception_sp_elx 213 214vector_entry irq_sp_elx 215 no_ret report_unhandled_interrupt 216 check_vector_size irq_sp_elx 217 218vector_entry fiq_sp_elx 219 no_ret report_unhandled_interrupt 220 check_vector_size fiq_sp_elx 221 222vector_entry serror_sp_elx 223 no_ret report_unhandled_exception 224 check_vector_size serror_sp_elx 225 226 /* --------------------------------------------------------------------- 227 * Lower EL using AArch64 : 0x400 - 0x600 228 * --------------------------------------------------------------------- 229 */ 230vector_entry sync_exception_aarch64 231 /* 232 * This exception vector will be the entry point for SMCs and traps 233 * that are unhandled at lower ELs most commonly. SP_EL3 should point 234 * to a valid cpu context where the general purpose and system register 235 * state can be saved. 236 */ 237 handle_sync_exception 238 check_vector_size sync_exception_aarch64 239 240vector_entry irq_aarch64 241 handle_interrupt_exception irq_aarch64 242 check_vector_size irq_aarch64 243 244vector_entry fiq_aarch64 245 handle_interrupt_exception fiq_aarch64 246 check_vector_size fiq_aarch64 247 248vector_entry serror_aarch64 249 /* 250 * SError exceptions from lower ELs are not currently supported. 251 * Report their occurrence. 252 */ 253 no_ret report_unhandled_exception 254 check_vector_size serror_aarch64 255 256 /* --------------------------------------------------------------------- 257 * Lower EL using AArch32 : 0x600 - 0x800 258 * --------------------------------------------------------------------- 259 */ 260vector_entry sync_exception_aarch32 261 /* 262 * This exception vector will be the entry point for SMCs and traps 263 * that are unhandled at lower ELs most commonly. SP_EL3 should point 264 * to a valid cpu context where the general purpose and system register 265 * state can be saved. 266 */ 267 handle_sync_exception 268 check_vector_size sync_exception_aarch32 269 270vector_entry irq_aarch32 271 handle_interrupt_exception irq_aarch32 272 check_vector_size irq_aarch32 273 274vector_entry fiq_aarch32 275 handle_interrupt_exception fiq_aarch32 276 check_vector_size fiq_aarch32 277 278vector_entry serror_aarch32 279 /* 280 * SError exceptions from lower ELs are not currently supported. 281 * Report their occurrence. 282 */ 283 no_ret report_unhandled_exception 284 check_vector_size serror_aarch32 285 286 287 /* --------------------------------------------------------------------- 288 * The following code handles secure monitor calls. 289 * Depending upon the execution state from where the SMC has been 290 * invoked, it frees some general purpose registers to perform the 291 * remaining tasks. They involve finding the runtime service handler 292 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 293 * before calling the handler. 294 * 295 * Note that x30 has been explicitly saved and can be used here 296 * --------------------------------------------------------------------- 297 */ 298func smc_handler 299smc_handler32: 300 /* Check whether aarch32 issued an SMC64 */ 301 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 302 303 /* 304 * Since we're are coming from aarch32, x8-x18 need to be saved as per 305 * SMC32 calling convention. If a lower EL in aarch64 is making an 306 * SMC32 call then it must have saved x8-x17 already therein. 307 */ 308 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 309 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 310 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 311 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 312 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 313 314 /* x4-x7, x18, sp_el0 are saved below */ 315 316smc_handler64: 317 /* 318 * Populate the parameters for the SMC handler. 319 * We already have x0-x4 in place. x5 will point to a cookie (not used 320 * now). x6 will point to the context structure (SP_EL3) and x7 will 321 * contain flags we need to pass to the handler Hence save x5-x7. 322 * 323 * Note: x4 only needs to be preserved for AArch32 callers but we do it 324 * for AArch64 callers as well for convenience 325 */ 326 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 327 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 328 329 /* Save rest of the gpregs and sp_el0*/ 330 save_x18_to_x29_sp_el0 331 332 mov x5, xzr 333 mov x6, sp 334 335 /* Get the unique owning entity number */ 336 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 337 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 338 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 339 340 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 341 342 /* Load descriptor index from array of indices */ 343 adr x14, rt_svc_descs_indices 344 ldrb w15, [x14, x16] 345 346 /* 347 * Restore the saved C runtime stack value which will become the new 348 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 349 * structure prior to the last ERET from EL3. 350 */ 351 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 352 353 /* 354 * Any index greater than 127 is invalid. Check bit 7 for 355 * a valid index 356 */ 357 tbnz w15, 7, smc_unknown 358 359 /* Switch to SP_EL0 */ 360 msr spsel, #0 361 362 /* 363 * Get the descriptor using the index 364 * x11 = (base + off), x15 = index 365 * 366 * handler = (base + off) + (index << log2(size)) 367 */ 368 lsl w10, w15, #RT_SVC_SIZE_LOG2 369 ldr x15, [x11, w10, uxtw] 370 371 /* 372 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 373 * switch during SMC handling. 374 * TODO: Revisit if all system registers can be saved later. 375 */ 376 mrs x16, spsr_el3 377 mrs x17, elr_el3 378 mrs x18, scr_el3 379 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 380 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 381 382 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 383 bfi x7, x18, #0, #1 384 385 mov sp, x12 386 387 /* 388 * Call the Secure Monitor Call handler and then drop directly into 389 * el3_exit() which will program any remaining architectural state 390 * prior to issuing the ERET to the desired lower EL. 391 */ 392#if DEBUG 393 cbz x15, rt_svc_fw_critical_error 394#endif 395 blr x15 396 397 b el3_exit 398 399smc_unknown: 400 /* 401 * Here we restore x4-x18 regardless of where we came from. AArch32 402 * callers will find the registers contents unchanged, but AArch64 403 * callers will find the registers modified (with stale earlier NS 404 * content). Either way, we aren't leaking any secure information 405 * through them. 406 */ 407 mov w0, #SMC_UNK 408 b restore_gp_registers_callee_eret 409 410smc_prohibited: 411 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 412 mov w0, #SMC_UNK 413 eret 414 415rt_svc_fw_critical_error: 416 /* Switch to SP_ELx */ 417 msr spsel, #1 418 no_ret report_unhandled_exception 419endfunc smc_handler 420