1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <context.h> 34#include <interrupt_mgmt.h> 35#include <platform_def.h> 36#include <runtime_svc.h> 37 38 .globl runtime_exceptions 39 40 /* ----------------------------------------------------- 41 * Handle SMC exceptions separately from other sync. 42 * exceptions. 43 * ----------------------------------------------------- 44 */ 45 .macro handle_sync_exception 46 /* Enable the SError interrupt */ 47 msr daifclr, #DAIF_ABT_BIT 48 49 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 50 mrs x30, esr_el3 51 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 52 53 cmp x30, #EC_AARCH32_SMC 54 b.eq smc_handler32 55 56 cmp x30, #EC_AARCH64_SMC 57 b.eq smc_handler64 58 59 /* ----------------------------------------------------- 60 * The following code handles any synchronous exception 61 * that is not an SMC. 62 * ----------------------------------------------------- 63 */ 64 65 bl report_unhandled_exception 66 .endm 67 68 69 /* ----------------------------------------------------- 70 * This macro handles FIQ or IRQ interrupts i.e. EL3, 71 * S-EL1 and NS interrupts. 72 * ----------------------------------------------------- 73 */ 74 .macro handle_interrupt_exception label 75 /* Enable the SError interrupt */ 76 msr daifclr, #DAIF_ABT_BIT 77 78 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 79 bl save_gp_registers 80 81 /* 82 * Save the EL3 system registers needed to return from 83 * this exception. 84 */ 85 mrs x0, spsr_el3 86 mrs x1, elr_el3 87 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 88 89 /* Switch to the runtime stack i.e. SP_EL0 */ 90 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 91 mov x20, sp 92 msr spsel, #0 93 mov sp, x2 94 95 /* 96 * Find out whether this is a valid interrupt type. If the 97 * interrupt controller reports a spurious interrupt then 98 * return to where we came from. 99 */ 100 bl plat_ic_get_pending_interrupt_type 101 cmp x0, #INTR_TYPE_INVAL 102 b.eq interrupt_exit_\label 103 104 /* 105 * Get the registered handler for this interrupt type. A 106 * NULL return value could be 'cause of the following 107 * conditions: 108 * 109 * a. An interrupt of a type was routed correctly but a 110 * handler for its type was not registered. 111 * 112 * b. An interrupt of a type was not routed correctly so 113 * a handler for its type was not registered. 114 * 115 * c. An interrupt of a type was routed correctly to EL3, 116 * but was deasserted before its pending state could 117 * be read. Another interrupt of a different type pended 118 * at the same time and its type was reported as pending 119 * instead. However, a handler for this type was not 120 * registered. 121 * 122 * a. and b. can only happen due to a programming error. 123 * The occurrence of c. could be beyond the control of 124 * Trusted Firmware. It makes sense to return from this 125 * exception instead of reporting an error. 126 */ 127 bl get_interrupt_type_handler 128 cbz x0, interrupt_exit_\label 129 mov x21, x0 130 131 mov x0, #INTR_ID_UNAVAILABLE 132 133 /* Set the current security state in the 'flags' parameter */ 134 mrs x2, scr_el3 135 ubfx x1, x2, #0, #1 136 137 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 138 mov x2, x20 139 140 /* x3 will point to a cookie (not used now) */ 141 mov x3, xzr 142 143 /* Call the interrupt type handler */ 144 blr x21 145 146interrupt_exit_\label: 147 /* Return from exception, possibly in a different security state */ 148 b el3_exit 149 150 .endm 151 152 153 .macro save_x18_to_x29_sp_el0 154 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 155 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 156 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 157 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 158 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 159 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 160 mrs x18, sp_el0 161 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 162 .endm 163 164 165vector_base runtime_exceptions 166 167 /* ----------------------------------------------------- 168 * Current EL with _sp_el0 : 0x0 - 0x200 169 * ----------------------------------------------------- 170 */ 171vector_entry sync_exception_sp_el0 172 /* ----------------------------------------------------- 173 * We don't expect any synchronous exceptions from EL3 174 * ----------------------------------------------------- 175 */ 176 bl report_unhandled_exception 177 check_vector_size sync_exception_sp_el0 178 179 /* ----------------------------------------------------- 180 * EL3 code is non-reentrant. Any asynchronous exception 181 * is a serious error. Loop infinitely. 182 * ----------------------------------------------------- 183 */ 184vector_entry irq_sp_el0 185 bl report_unhandled_interrupt 186 check_vector_size irq_sp_el0 187 188 189vector_entry fiq_sp_el0 190 bl report_unhandled_interrupt 191 check_vector_size fiq_sp_el0 192 193 194vector_entry serror_sp_el0 195 bl report_unhandled_exception 196 check_vector_size serror_sp_el0 197 198 /* ----------------------------------------------------- 199 * Current EL with SPx: 0x200 - 0x400 200 * ----------------------------------------------------- 201 */ 202 203vector_entry sync_exception_sp_elx 204 /* ----------------------------------------------------- 205 * This exception will trigger if anything went wrong 206 * during a previous exception entry or exit or while 207 * handling an earlier unexpected synchronous exception. 208 * There is a high probability that SP_EL3 is corrupted. 209 * ----------------------------------------------------- 210 */ 211 bl report_unhandled_exception 212 check_vector_size sync_exception_sp_elx 213 214vector_entry irq_sp_elx 215 bl report_unhandled_interrupt 216 check_vector_size irq_sp_elx 217 218vector_entry fiq_sp_elx 219 bl report_unhandled_interrupt 220 check_vector_size fiq_sp_elx 221 222vector_entry serror_sp_elx 223 bl report_unhandled_exception 224 check_vector_size serror_sp_elx 225 226 /* ----------------------------------------------------- 227 * Lower EL using AArch64 : 0x400 - 0x600 228 * ----------------------------------------------------- 229 */ 230vector_entry sync_exception_aarch64 231 /* ----------------------------------------------------- 232 * This exception vector will be the entry point for 233 * SMCs and traps that are unhandled at lower ELs most 234 * commonly. SP_EL3 should point to a valid cpu context 235 * where the general purpose and system register state 236 * can be saved. 237 * ----------------------------------------------------- 238 */ 239 handle_sync_exception 240 check_vector_size sync_exception_aarch64 241 242 /* ----------------------------------------------------- 243 * Asynchronous exceptions from lower ELs are not 244 * currently supported. Report their occurrence. 245 * ----------------------------------------------------- 246 */ 247vector_entry irq_aarch64 248 handle_interrupt_exception irq_aarch64 249 check_vector_size irq_aarch64 250 251vector_entry fiq_aarch64 252 handle_interrupt_exception fiq_aarch64 253 check_vector_size fiq_aarch64 254 255vector_entry serror_aarch64 256 bl report_unhandled_exception 257 check_vector_size serror_aarch64 258 259 /* ----------------------------------------------------- 260 * Lower EL using AArch32 : 0x600 - 0x800 261 * ----------------------------------------------------- 262 */ 263vector_entry sync_exception_aarch32 264 /* ----------------------------------------------------- 265 * This exception vector will be the entry point for 266 * SMCs and traps that are unhandled at lower ELs most 267 * commonly. SP_EL3 should point to a valid cpu context 268 * where the general purpose and system register state 269 * can be saved. 270 * ----------------------------------------------------- 271 */ 272 handle_sync_exception 273 check_vector_size sync_exception_aarch32 274 275 /* ----------------------------------------------------- 276 * Asynchronous exceptions from lower ELs are not 277 * currently supported. Report their occurrence. 278 * ----------------------------------------------------- 279 */ 280vector_entry irq_aarch32 281 handle_interrupt_exception irq_aarch32 282 check_vector_size irq_aarch32 283 284vector_entry fiq_aarch32 285 handle_interrupt_exception fiq_aarch32 286 check_vector_size fiq_aarch32 287 288vector_entry serror_aarch32 289 bl report_unhandled_exception 290 check_vector_size serror_aarch32 291 292 293 /* ----------------------------------------------------- 294 * The following code handles secure monitor calls. 295 * Depending upon the execution state from where the SMC 296 * has been invoked, it frees some general purpose 297 * registers to perform the remaining tasks. They 298 * involve finding the runtime service handler that is 299 * the target of the SMC & switching to runtime stacks 300 * (SP_EL0) before calling the handler. 301 * 302 * Note that x30 has been explicitly saved and can be 303 * used here 304 * ----------------------------------------------------- 305 */ 306func smc_handler 307smc_handler32: 308 /* Check whether aarch32 issued an SMC64 */ 309 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 310 311 /* ----------------------------------------------------- 312 * Since we're are coming from aarch32, x8-x18 need to 313 * be saved as per SMC32 calling convention. If a lower 314 * EL in aarch64 is making an SMC32 call then it must 315 * have saved x8-x17 already therein. 316 * ----------------------------------------------------- 317 */ 318 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 319 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 320 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 321 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 322 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 323 324 /* x4-x7, x18, sp_el0 are saved below */ 325 326smc_handler64: 327 /* ----------------------------------------------------- 328 * Populate the parameters for the SMC handler. We 329 * already have x0-x4 in place. x5 will point to a 330 * cookie (not used now). x6 will point to the context 331 * structure (SP_EL3) and x7 will contain flags we need 332 * to pass to the handler Hence save x5-x7. Note that x4 333 * only needs to be preserved for AArch32 callers but we 334 * do it for AArch64 callers as well for convenience 335 * ----------------------------------------------------- 336 */ 337 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 338 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 339 340 /* Save rest of the gpregs and sp_el0*/ 341 save_x18_to_x29_sp_el0 342 343 mov x5, xzr 344 mov x6, sp 345 346 /* Get the unique owning entity number */ 347 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 348 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 349 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 350 351 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 352 353 /* Load descriptor index from array of indices */ 354 adr x14, rt_svc_descs_indices 355 ldrb w15, [x14, x16] 356 357 /* ----------------------------------------------------- 358 * Restore the saved C runtime stack value which will 359 * become the new SP_EL0 i.e. EL3 runtime stack. It was 360 * saved in the 'cpu_context' structure prior to the last 361 * ERET from EL3. 362 * ----------------------------------------------------- 363 */ 364 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 365 366 /* 367 * Any index greater than 127 is invalid. Check bit 7 for 368 * a valid index 369 */ 370 tbnz w15, 7, smc_unknown 371 372 /* Switch to SP_EL0 */ 373 msr spsel, #0 374 375 /* ----------------------------------------------------- 376 * Get the descriptor using the index 377 * x11 = (base + off), x15 = index 378 * 379 * handler = (base + off) + (index << log2(size)) 380 * ----------------------------------------------------- 381 */ 382 lsl w10, w15, #RT_SVC_SIZE_LOG2 383 ldr x15, [x11, w10, uxtw] 384 385 /* ----------------------------------------------------- 386 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 387 * is a world switch during SMC handling. 388 * TODO: Revisit if all system registers can be saved 389 * later. 390 * ----------------------------------------------------- 391 */ 392 mrs x16, spsr_el3 393 mrs x17, elr_el3 394 mrs x18, scr_el3 395 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 396 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 397 398 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 399 bfi x7, x18, #0, #1 400 401 mov sp, x12 402 403 /* ----------------------------------------------------- 404 * Call the Secure Monitor Call handler and then drop 405 * directly into el3_exit() which will program any 406 * remaining architectural state prior to issuing the 407 * ERET to the desired lower EL. 408 * ----------------------------------------------------- 409 */ 410#if DEBUG 411 cbz x15, rt_svc_fw_critical_error 412#endif 413 blr x15 414 415 b el3_exit 416 417smc_unknown: 418 /* 419 * Here we restore x4-x18 regardless of where we came from. AArch32 420 * callers will find the registers contents unchanged, but AArch64 421 * callers will find the registers modified (with stale earlier NS 422 * content). Either way, we aren't leaking any secure information 423 * through them 424 */ 425 mov w0, #SMC_UNK 426 b restore_gp_registers_callee_eret 427 428smc_prohibited: 429 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 430 mov w0, #SMC_UNK 431 eret 432 433rt_svc_fw_critical_error: 434 msr spsel, #1 /* Switch to SP_ELx */ 435 bl report_unhandled_exception 436endfunc smc_handler 437