xref: /rk3399_ARM-atf/bl31/aarch64/runtime_exceptions.S (revision 401607cf31ca8a752ee3154d45b69ee4995a8923) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <cm_macros.S>
34#include <context.h>
35#include <platform.h>
36#include <runtime_svc.h>
37
38	.globl	runtime_exceptions
39	.globl	el3_exit
40	.globl	get_exception_stack
41
42	.macro save_x18_to_x29_sp_el0
43	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
44	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
45	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
46	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
47	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
48	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
49	mrs	x18, sp_el0
50	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
51	.endm
52
53	.section	.vectors, "ax"; .align 11
54
55	.align	7
56runtime_exceptions:
57	/* -----------------------------------------------------
58	 * Current EL with _sp_el0 : 0x0 - 0x180
59	 * -----------------------------------------------------
60	 */
61sync_exception_sp_el0:
62	/* -----------------------------------------------------
63	 * We don't expect any synchronous exceptions from EL3
64	 * -----------------------------------------------------
65	 */
66	wfi
67	b	sync_exception_sp_el0
68	check_vector_size sync_exception_sp_el0
69
70	.align	7
71	/* -----------------------------------------------------
72	 * EL3 code is non-reentrant. Any asynchronous exception
73	 * is a serious error. Loop infinitely.
74	 * -----------------------------------------------------
75	 */
76irq_sp_el0:
77	handle_async_exception IRQ_SP_EL0
78	b	irq_sp_el0
79	check_vector_size irq_sp_el0
80
81	.align	7
82fiq_sp_el0:
83	handle_async_exception FIQ_SP_EL0
84	b	fiq_sp_el0
85	check_vector_size fiq_sp_el0
86
87	.align	7
88serror_sp_el0:
89	handle_async_exception SERROR_SP_EL0
90	b	serror_sp_el0
91	check_vector_size serror_sp_el0
92
93	/* -----------------------------------------------------
94	 * Current EL with SPx: 0x200 - 0x380
95	 * -----------------------------------------------------
96	 */
97	.align	7
98sync_exception_sp_elx:
99	/* -----------------------------------------------------
100	 * This exception will trigger if anything went wrong
101	 * during a previous exception entry or exit or while
102	 * handling an earlier unexpected synchronous exception.
103	 * In any case we cannot rely on SP_EL3. Switching to a
104	 * known safe area of memory will corrupt at least a
105	 * single register. It is best to enter wfi in loop as
106	 * that will preserve the system state for analysis
107	 * through a debugger later.
108	 * -----------------------------------------------------
109	 */
110	wfi
111	b	sync_exception_sp_elx
112	check_vector_size sync_exception_sp_elx
113
114	/* -----------------------------------------------------
115	 * As mentioned in the previous comment, all bets are
116	 * off if SP_EL3 cannot be relied upon. Report their
117	 * occurrence.
118	 * -----------------------------------------------------
119	 */
120	.align	7
121irq_sp_elx:
122	b	irq_sp_elx
123	check_vector_size irq_sp_elx
124
125	.align	7
126fiq_sp_elx:
127	b	fiq_sp_elx
128	check_vector_size fiq_sp_elx
129
130	.align	7
131serror_sp_elx:
132	b	serror_sp_elx
133	check_vector_size serror_sp_elx
134
135	/* -----------------------------------------------------
136	 * Lower EL using AArch64 : 0x400 - 0x580
137	 * -----------------------------------------------------
138	 */
139	.align	7
140sync_exception_aarch64:
141	/* -----------------------------------------------------
142	 * This exception vector will be the entry point for
143	 * SMCs and traps that are unhandled at lower ELs most
144	 * commonly. SP_EL3 should point to a valid cpu context
145	 * where the general purpose and system register state
146	 * can be saved.
147	 * -----------------------------------------------------
148	 */
149	handle_sync_exception
150	check_vector_size sync_exception_aarch64
151
152	.align	7
153	/* -----------------------------------------------------
154	 * Asynchronous exceptions from lower ELs are not
155	 * currently supported. Report their occurrence.
156	 * -----------------------------------------------------
157	 */
158irq_aarch64:
159	handle_async_exception IRQ_AARCH64
160	b	irq_aarch64
161	check_vector_size irq_aarch64
162
163	.align	7
164fiq_aarch64:
165	handle_async_exception FIQ_AARCH64
166	b	fiq_aarch64
167	check_vector_size fiq_aarch64
168
169	.align	7
170serror_aarch64:
171	handle_async_exception SERROR_AARCH64
172	b	serror_aarch64
173	check_vector_size serror_aarch64
174
175	/* -----------------------------------------------------
176	 * Lower EL using AArch32 : 0x600 - 0x780
177	 * -----------------------------------------------------
178	 */
179	.align	7
180sync_exception_aarch32:
181	/* -----------------------------------------------------
182	 * This exception vector will be the entry point for
183	 * SMCs and traps that are unhandled at lower ELs most
184	 * commonly. SP_EL3 should point to a valid cpu context
185	 * where the general purpose and system register state
186	 * can be saved.
187	 * -----------------------------------------------------
188	 */
189	handle_sync_exception
190	check_vector_size sync_exception_aarch32
191
192	.align	7
193	/* -----------------------------------------------------
194	 * Asynchronous exceptions from lower ELs are not
195	 * currently supported. Report their occurrence.
196	 * -----------------------------------------------------
197	 */
198irq_aarch32:
199	handle_async_exception IRQ_AARCH32
200	b	irq_aarch32
201	check_vector_size irq_aarch32
202
203	.align	7
204fiq_aarch32:
205	handle_async_exception FIQ_AARCH32
206	b	fiq_aarch32
207	check_vector_size fiq_aarch32
208
209	.align	7
210serror_aarch32:
211	handle_async_exception SERROR_AARCH32
212	b	serror_aarch32
213	check_vector_size serror_aarch32
214
215	.align	7
216
217	/* -----------------------------------------------------
218	 * The following code handles secure monitor calls.
219	 * Depending upon the execution state from where the SMC
220	 * has been invoked, it frees some general purpose
221	 * registers to perform the remaining tasks. They
222	 * involve finding the runtime service handler that is
223	 * the target of the SMC & switching to runtime stacks
224	 * (SP_EL0) before calling the handler.
225	 *
226	 * Note that x30 has been explicitly saved and can be
227	 * used here
228	 * -----------------------------------------------------
229	 */
230func smc_handler
231smc_handler32:
232	/* Check whether aarch32 issued an SMC64 */
233	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
234
235	/* -----------------------------------------------------
236	 * Since we're are coming from aarch32, x8-x18 need to
237	 * be saved as per SMC32 calling convention. If a lower
238	 * EL in aarch64 is making an SMC32 call then it must
239	 * have saved x8-x17 already therein.
240	 * -----------------------------------------------------
241	 */
242	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
243	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
244	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
245	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
246	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
247
248	/* x4-x7, x18, sp_el0 are saved below */
249
250smc_handler64:
251	/* -----------------------------------------------------
252	 * Populate the parameters for the SMC handler. We
253	 * already have x0-x4 in place. x5 will point to a
254	 * cookie (not used now). x6 will point to the context
255	 * structure (SP_EL3) and x7 will contain flags we need
256	 * to pass to the handler Hence save x5-x7. Note that x4
257	 * only needs to be preserved for AArch32 callers but we
258	 * do it for AArch64 callers as well for convenience
259	 * -----------------------------------------------------
260	 */
261	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
262	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
263
264	/* Save rest of the gpregs and sp_el0*/
265	save_x18_to_x29_sp_el0
266
267	mov	x5, xzr
268	mov	x6, sp
269
270	/* Get the unique owning entity number */
271	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
272	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
273	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
274
275	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
276
277	/* Load descriptor index from array of indices */
278	adr	x14, rt_svc_descs_indices
279	ldrb	w15, [x14, x16]
280
281	/* -----------------------------------------------------
282	 * Restore the saved C runtime stack value which will
283	 * become the new SP_EL0 i.e. EL3 runtime stack. It was
284	 * saved in the 'cpu_context' structure prior to the last
285	 * ERET from EL3.
286	 * -----------------------------------------------------
287	 */
288	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
289
290	/*
291	 * Any index greater than 127 is invalid. Check bit 7 for
292	 * a valid index
293	 */
294	tbnz	w15, 7, smc_unknown
295
296	/* Switch to SP_EL0 */
297	msr	spsel, #0
298
299	/* -----------------------------------------------------
300	 * Get the descriptor using the index
301	 * x11 = (base + off), x15 = index
302	 *
303	 * handler = (base + off) + (index << log2(size))
304	 * -----------------------------------------------------
305	 */
306	lsl	w10, w15, #RT_SVC_SIZE_LOG2
307	ldr	x15, [x11, w10, uxtw]
308
309	/* -----------------------------------------------------
310	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
311	 * is a world switch during SMC handling.
312	 * TODO: Revisit if all system registers can be saved
313	 * later.
314	 * -----------------------------------------------------
315	 */
316	mrs	x16, spsr_el3
317	mrs	x17, elr_el3
318	mrs	x18, scr_el3
319	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
320	stp	x18, xzr, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
321
322	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
323	bfi	x7, x18, #0, #1
324
325	mov	sp, x12
326
327	/* -----------------------------------------------------
328	 * Call the Secure Monitor Call handler and then drop
329	 * directly into el3_exit() which will program any
330	 * remaining architectural state prior to issuing the
331	 * ERET to the desired lower EL.
332	 * -----------------------------------------------------
333	 */
334#if DEBUG
335	cbz	x15, rt_svc_fw_critical_error
336#endif
337	blr	x15
338
339	/* -----------------------------------------------------
340	 * This routine assumes that the SP_EL3 is pointing to
341	 * a valid context structure from where the gp regs and
342	 * other special registers can be retrieved.
343	 *
344	 * Keep it in the same section as smc_handler as this
345	 * function uses a fall-through to el3_exit
346	 * -----------------------------------------------------
347	 */
348el3_exit: ; .type el3_exit, %function
349	/* -----------------------------------------------------
350	 * Save the current SP_EL0 i.e. the EL3 runtime stack
351	 * which will be used for handling the next SMC. Then
352	 * switch to SP_EL3
353	 * -----------------------------------------------------
354	 */
355	mov	x17, sp
356	msr	spsel, #1
357	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
358
359	/* -----------------------------------------------------
360	 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
361	 * -----------------------------------------------------
362	 */
363	ldp	x18, xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
364	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
365	msr	scr_el3, x18
366	msr	spsr_el3, x16
367	msr	elr_el3, x17
368
369	/* Restore saved general purpose registers and return */
370	bl	restore_gp_registers
371	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
372	eret
373
374smc_unknown:
375	/*
376	 * Here we restore x4-x18 regardless of where we came from. AArch32
377	 * callers will find the registers contents unchanged, but AArch64
378	 * callers will find the registers modified (with stale earlier NS
379	 * content). Either way, we aren't leaking any secure information
380	 * through them
381	 */
382	bl	restore_gp_registers_callee
383
384smc_prohibited:
385	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
386	mov	w0, #SMC_UNK
387	eret
388
389rt_svc_fw_critical_error:
390	b	rt_svc_fw_critical_error
391
392	/* -----------------------------------------------------
393	 * The following functions are used to saved and restore
394	 * all the general pupose registers. Ideally we would
395	 * only save and restore the callee saved registers when
396	 * a world switch occurs but that type of implementation
397	 * is more complex. So currently we will always save and
398	 * restore these registers on entry and exit of EL3.
399	 * These are not macros to ensure their invocation fits
400	 * within the 32 instructions per exception vector.
401	 * -----------------------------------------------------
402	 */
403func save_gp_registers
404	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
405	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
406	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
407	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
408	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
409	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
410	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
411	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
412	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
413	save_x18_to_x29_sp_el0
414	ret
415
416func restore_gp_registers
417	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
418	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
419
420restore_gp_registers_callee:
421	ldr	x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
422
423	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
424	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
425	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
426	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
427	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
428	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
429	msr	sp_el0, x17
430	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
431	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
432	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
433	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
434	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
435	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
436	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
437	ret
438
439	/* -----------------------------------------------------
440	 * 256 bytes of exception stack for each cpu
441	 * -----------------------------------------------------
442	 */
443#if DEBUG
444#define PCPU_EXCEPTION_STACK_SIZE	0x300
445#else
446#define PCPU_EXCEPTION_STACK_SIZE	0x100
447#endif
448	/* -----------------------------------------------------
449	 * void get_exception_stack (uint64_t mpidr) : This
450	 * function is used to allocate a small stack for
451	 * reporting unhandled exceptions
452	 * -----------------------------------------------------
453	 */
454func get_exception_stack
455	mov	x10, x30 // lr
456	get_mp_stack pcpu_exception_stack, PCPU_EXCEPTION_STACK_SIZE
457	ret	x10
458
459	/* -----------------------------------------------------
460	 * Per-cpu exception stacks in normal memory.
461	 * -----------------------------------------------------
462	 */
463declare_stack pcpu_exception_stack, tzfw_normal_stacks, \
464		PCPU_EXCEPTION_STACK_SIZE, PLATFORM_CORE_COUNT
465