1/* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 9#include <assert_macros.S> 10#include <asm_macros.S> 11#include <assert_macros.S> 12#include <bl31/ea_handle.h> 13#include <context.h> 14#include <lib/extensions/ras_arch.h> 15#include <cpu_macros.S> 16#include <context.h> 17 18 .globl handle_lower_el_ea_esb 19 .globl handle_lower_el_sync_ea 20 .globl handle_lower_el_async_ea 21 22 23/* 24 * Function to delegate External Aborts synchronized by ESB instruction at EL3 25 * vector entry. This function assumes GP registers x0-x29 have been saved, and 26 * are available for use. It delegates the handling of the EA to platform 27 * handler, and returns only upon successfully handling the EA; otherwise 28 * panics. On return from this function, the original exception handler is 29 * expected to resume. 30 */ 31func handle_lower_el_ea_esb 32 mov x0, #ERROR_EA_ESB 33 mrs x1, DISR_EL1 34 b ea_proceed 35endfunc handle_lower_el_ea_esb 36 37 38/* 39 * This function forms the tail end of Synchronous Exception entry from lower 40 * EL, and expects to handle Synchronous External Aborts from lower EL and CPU 41 * Implementation Defined Exceptions. If any other kind of exception is detected, 42 * then this function reports unhandled exception. 43 * 44 * It delegates the handling of the EA to platform handler, and upon successfully 45 * handling the EA, exits EL3; otherwise panics. 46 * 47 * This function assumes x30 has been saved. 48 */ 49func handle_lower_el_sync_ea 50 mrs x30, esr_el3 51 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 52 53 /* Check for I/D aborts from lower EL */ 54 cmp x30, #EC_IABORT_LOWER_EL 55 b.eq 1f 56 57 cmp x30, #EC_DABORT_LOWER_EL 58 b.eq 1f 59 60 /* Save GP registers */ 61 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 62 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 63 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 64 65 /* Get the cpu_ops pointer */ 66 bl get_cpu_ops_ptr 67 68 /* Get the cpu_ops exception handler */ 69 ldr x0, [x0, #CPU_E_HANDLER_FUNC] 70 71 /* 72 * If the reserved function pointer is NULL, this CPU does not have an 73 * implementation defined exception handler function 74 */ 75 cbz x0, 2f 76 mrs x1, esr_el3 77 ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH 78 blr x0 79 b 2f 80 811: 82 /* 83 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 84 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 85 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 86 * Also set the PSTATE to a known state. 87 */ 88 bl prepare_el3_entry 89 90#if ENABLE_PAUTH 91 /* Load and program APIAKey firmware key */ 92 bl pauth_load_bl31_apiakey 93#endif 94 95 /* Setup exception class and syndrome arguments for platform handler */ 96 mov x0, #ERROR_EA_SYNC 97 mrs x1, esr_el3 98 bl delegate_sync_ea 99 100 /* el3_exit assumes SP_EL0 on entry */ 101 msr spsel, #MODE_SP_EL0 102 b el3_exit 1032: 104 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 105 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 106 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 107 108 /* Synchronous exceptions other than the above are assumed to be EA */ 109 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 110 no_ret report_unhandled_exception 111endfunc handle_lower_el_sync_ea 112 113 114/* 115 * This function handles SErrors from lower ELs. 116 * 117 * It delegates the handling of the EA to platform handler, and upon successfully 118 * handling the EA, exits EL3; otherwise panics. 119 * 120 * This function assumes x30 has been saved. 121 */ 122func handle_lower_el_async_ea 123 124 /* 125 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 126 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 127 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 128 * Also set the PSTATE to a known state. 129 */ 130 bl prepare_el3_entry 131 132#if ENABLE_PAUTH 133 /* Load and program APIAKey firmware key */ 134 bl pauth_load_bl31_apiakey 135#endif 136 137 /* Setup exception class and syndrome arguments for platform handler */ 138 mov x0, #ERROR_EA_ASYNC 139 mrs x1, esr_el3 140 bl delegate_async_ea 141 142 /* el3_exit assumes SP_EL0 on entry */ 143 msr spsel, #MODE_SP_EL0 144 b el3_exit 145endfunc handle_lower_el_async_ea 146 147 148/* 149 * Prelude for Synchronous External Abort handling. This function assumes that 150 * all GP registers have been saved by the caller. 151 * 152 * x0: EA reason 153 * x1: EA syndrome 154 */ 155func delegate_sync_ea 156#if RAS_EXTENSION 157 /* 158 * Check for Uncontainable error type. If so, route to the platform 159 * fatal error handler rather than the generic EA one. 160 */ 161 ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH 162 cmp x2, #ERROR_STATUS_SET_UC 163 b.ne 1f 164 165 /* Check fault status code */ 166 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 167 cmp x3, #SYNC_EA_FSC 168 b.ne 1f 169 170 no_ret plat_handle_uncontainable_ea 1711: 172#endif 173 174 b ea_proceed 175endfunc delegate_sync_ea 176 177 178/* 179 * Prelude for Asynchronous External Abort handling. This function assumes that 180 * all GP registers have been saved by the caller. 181 * 182 * x0: EA reason 183 * x1: EA syndrome 184 */ 185func delegate_async_ea 186#if RAS_EXTENSION 187 /* Check Exception Class to ensure SError, as this function should 188 * only be invoked for SError. If that is not the case, which implies 189 * either an HW error or programming error, panic. 190 */ 191 ubfx x2, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH 192 cmp x2, EC_SERROR 193 b.ne el3_panic 194 /* 195 * Check for Implementation Defined Syndrome. If so, skip checking 196 * Uncontainable error type from the syndrome as the format is unknown. 197 */ 198 tbnz x1, #SERROR_IDS_BIT, 1f 199 200 /* AET only valid when DFSC is 0x11 */ 201 ubfx x2, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 202 cmp x2, #DFSC_SERROR 203 b.ne 1f 204 205 /* 206 * Check for Uncontainable error type. If so, route to the platform 207 * fatal error handler rather than the generic EA one. 208 */ 209 ubfx x3, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH 210 cmp x3, #ERROR_STATUS_UET_UC 211 b.ne 1f 212 213 no_ret plat_handle_uncontainable_ea 2141: 215#endif 216 217 b ea_proceed 218endfunc delegate_async_ea 219 220 221/* 222 * Delegate External Abort handling to platform's EA handler. This function 223 * assumes that all GP registers have been saved by the caller. 224 * 225 * x0: EA reason 226 * x1: EA syndrome 227 */ 228func ea_proceed 229 /* 230 * If the ESR loaded earlier is not zero, we were processing an EA 231 * already, and this is a double fault. 232 */ 233 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 234 cbz x5, 1f 235 no_ret plat_handle_double_fault 236 2371: 238 /* Save EL3 state */ 239 mrs x2, spsr_el3 240 mrs x3, elr_el3 241 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 242 243 /* 244 * Save ESR as handling might involve lower ELs, and returning back to 245 * EL3 from there would trample the original ESR. 246 */ 247 mrs x4, scr_el3 248 mrs x5, esr_el3 249 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 250 251 /* 252 * Setup rest of arguments, and call platform External Abort handler. 253 * 254 * x0: EA reason (already in place) 255 * x1: Exception syndrome (already in place). 256 * x2: Cookie (unused for now). 257 * x3: Context pointer. 258 * x4: Flags (security state from SCR for now). 259 */ 260 mov x2, xzr 261 mov x3, sp 262 ubfx x4, x4, #0, #1 263 264 /* Switch to runtime stack */ 265 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 266 msr spsel, #MODE_SP_EL0 267 mov sp, x5 268 269 mov x29, x30 270#if ENABLE_ASSERTIONS 271 /* Stash the stack pointer */ 272 mov x28, sp 273#endif 274 bl plat_ea_handler 275 276#if ENABLE_ASSERTIONS 277 /* 278 * Error handling flows might involve long jumps; so upon returning from 279 * the platform error handler, validate that the we've completely 280 * unwound the stack. 281 */ 282 mov x27, sp 283 cmp x28, x27 284 ASM_ASSERT(eq) 285#endif 286 287 /* Make SP point to context */ 288 msr spsel, #MODE_SP_ELX 289 290 /* Restore EL3 state and ESR */ 291 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 292 msr spsr_el3, x1 293 msr elr_el3, x2 294 295 /* Restore ESR_EL3 and SCR_EL3 */ 296 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 297 msr scr_el3, x3 298 msr esr_el3, x4 299 300#if ENABLE_ASSERTIONS 301 cmp x4, xzr 302 ASM_ASSERT(ne) 303#endif 304 305 /* Clear ESR storage */ 306 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 307 308 ret x29 309endfunc ea_proceed 310