1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8#include <assert_macros.S> 9#include <asm_macros.S> 10#include <assert_macros.S> 11#include <bl31/ea_handle.h> 12#include <context.h> 13#include <lib/extensions/ras_arch.h> 14#include <cpu_macros.S> 15#include <context.h> 16 17 .globl handle_lower_el_ea_esb 18 .globl enter_lower_el_sync_ea 19 .globl enter_lower_el_async_ea 20 21 22/* 23 * Function to delegate External Aborts synchronized by ESB instruction at EL3 24 * vector entry. This function assumes GP registers x0-x29 have been saved, and 25 * are available for use. It delegates the handling of the EA to platform 26 * handler, and returns only upon successfully handling the EA; otherwise 27 * panics. On return from this function, the original exception handler is 28 * expected to resume. 29 */ 30func handle_lower_el_ea_esb 31 mov x0, #ERROR_EA_ESB 32 mrs x1, DISR_EL1 33 b ea_proceed 34endfunc handle_lower_el_ea_esb 35 36 37/* 38 * This function forms the tail end of Synchronous Exception entry from lower 39 * EL, and expects to handle Synchronous External Aborts from lower EL and CPU 40 * Implementation Defined Exceptions. If any other kind of exception is detected, 41 * then this function reports unhandled exception. 42 * 43 * Since it's part of exception vector, this function doesn't expect any GP 44 * registers to have been saved. It delegates the handling of the EA to platform 45 * handler, and upon successfully handling the EA, exits EL3; otherwise panics. 46 */ 47func enter_lower_el_sync_ea 48 /* 49 * Explicitly save x30 so as to free up a register and to enable 50 * branching. 51 */ 52 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 53 54 mrs x30, esr_el3 55 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 56 57 /* Check for I/D aborts from lower EL */ 58 cmp x30, #EC_IABORT_LOWER_EL 59 b.eq 1f 60 61 cmp x30, #EC_DABORT_LOWER_EL 62 b.eq 1f 63 64 /* Save GP registers */ 65 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 66 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 67 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 68 69 /* Get the cpu_ops pointer */ 70 bl get_cpu_ops_ptr 71 72 /* Get the cpu_ops exception handler */ 73 ldr x0, [x0, #CPU_E_HANDLER_FUNC] 74 75 /* 76 * If the reserved function pointer is NULL, this CPU does not have an 77 * implementation defined exception handler function 78 */ 79 cbz x0, 2f 80 mrs x1, esr_el3 81 ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH 82 blr x0 83 b 2f 84 851: 86 /* Test for EA bit in the instruction syndrome */ 87 mrs x30, esr_el3 88 tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f 89 90 /* 91 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 92 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 93 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 94 */ 95 bl save_gp_pmcr_pauth_regs 96 97#if ENABLE_PAUTH 98 /* Load and program APIAKey firmware key */ 99 bl pauth_load_bl31_apiakey 100#endif 101 102 /* Setup exception class and syndrome arguments for platform handler */ 103 mov x0, #ERROR_EA_SYNC 104 mrs x1, esr_el3 105 adr x30, el3_exit 106 b delegate_sync_ea 107 1082: 109 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 110 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 111 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 112 1133: 114 /* Synchronous exceptions other than the above are assumed to be EA */ 115 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 116 no_ret report_unhandled_exception 117endfunc enter_lower_el_sync_ea 118 119 120/* 121 * This function handles SErrors from lower ELs. 122 * 123 * Since it's part of exception vector, this function doesn't expect any GP 124 * registers to have been saved. It delegates the handling of the EA to platform 125 * handler, and upon successfully handling the EA, exits EL3; otherwise panics. 126 */ 127func enter_lower_el_async_ea 128 /* 129 * Explicitly save x30 so as to free up a register and to enable 130 * branching 131 */ 132 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 133 134 /* 135 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 136 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 137 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 138 */ 139 bl save_gp_pmcr_pauth_regs 140 141#if ENABLE_PAUTH 142 /* Load and program APIAKey firmware key */ 143 bl pauth_load_bl31_apiakey 144#endif 145 146 /* Setup exception class and syndrome arguments for platform handler */ 147 mov x0, #ERROR_EA_ASYNC 148 mrs x1, esr_el3 149 adr x30, el3_exit 150 b delegate_async_ea 151endfunc enter_lower_el_async_ea 152 153 154/* 155 * Prelude for Synchronous External Abort handling. This function assumes that 156 * all GP registers have been saved by the caller. 157 * 158 * x0: EA reason 159 * x1: EA syndrome 160 */ 161func delegate_sync_ea 162#if RAS_EXTENSION 163 /* 164 * Check for Uncontainable error type. If so, route to the platform 165 * fatal error handler rather than the generic EA one. 166 */ 167 ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH 168 cmp x2, #ERROR_STATUS_SET_UC 169 b.ne 1f 170 171 /* Check fault status code */ 172 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 173 cmp x3, #SYNC_EA_FSC 174 b.ne 1f 175 176 no_ret plat_handle_uncontainable_ea 1771: 178#endif 179 180 b ea_proceed 181endfunc delegate_sync_ea 182 183 184/* 185 * Prelude for Asynchronous External Abort handling. This function assumes that 186 * all GP registers have been saved by the caller. 187 * 188 * x0: EA reason 189 * x1: EA syndrome 190 */ 191func delegate_async_ea 192#if RAS_EXTENSION 193 /* 194 * Check for Implementation Defined Syndrome. If so, skip checking 195 * Uncontainable error type from the syndrome as the format is unknown. 196 */ 197 tbnz x1, #SERROR_IDS_BIT, 1f 198 199 /* 200 * Check for Uncontainable error type. If so, route to the platform 201 * fatal error handler rather than the generic EA one. 202 */ 203 ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH 204 cmp x2, #ERROR_STATUS_UET_UC 205 b.ne 1f 206 207 /* Check DFSC for SError type */ 208 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 209 cmp x3, #DFSC_SERROR 210 b.ne 1f 211 212 no_ret plat_handle_uncontainable_ea 2131: 214#endif 215 216 b ea_proceed 217endfunc delegate_async_ea 218 219 220/* 221 * Delegate External Abort handling to platform's EA handler. This function 222 * assumes that all GP registers have been saved by the caller. 223 * 224 * x0: EA reason 225 * x1: EA syndrome 226 */ 227func ea_proceed 228 /* 229 * If the ESR loaded earlier is not zero, we were processing an EA 230 * already, and this is a double fault. 231 */ 232 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 233 cbz x5, 1f 234 no_ret plat_handle_double_fault 235 2361: 237 /* Save EL3 state */ 238 mrs x2, spsr_el3 239 mrs x3, elr_el3 240 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 241 242 /* 243 * Save ESR as handling might involve lower ELs, and returning back to 244 * EL3 from there would trample the original ESR. 245 */ 246 mrs x4, scr_el3 247 mrs x5, esr_el3 248 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 249 250 /* 251 * Setup rest of arguments, and call platform External Abort handler. 252 * 253 * x0: EA reason (already in place) 254 * x1: Exception syndrome (already in place). 255 * x2: Cookie (unused for now). 256 * x3: Context pointer. 257 * x4: Flags (security state from SCR for now). 258 */ 259 mov x2, xzr 260 mov x3, sp 261 ubfx x4, x4, #0, #1 262 263 /* Switch to runtime stack */ 264 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 265 msr spsel, #MODE_SP_EL0 266 mov sp, x5 267 268 mov x29, x30 269#if ENABLE_ASSERTIONS 270 /* Stash the stack pointer */ 271 mov x28, sp 272#endif 273 bl plat_ea_handler 274 275#if ENABLE_ASSERTIONS 276 /* 277 * Error handling flows might involve long jumps; so upon returning from 278 * the platform error handler, validate that the we've completely 279 * unwound the stack. 280 */ 281 mov x27, sp 282 cmp x28, x27 283 ASM_ASSERT(eq) 284#endif 285 286 /* Make SP point to context */ 287 msr spsel, #MODE_SP_ELX 288 289 /* Restore EL3 state and ESR */ 290 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 291 msr spsr_el3, x1 292 msr elr_el3, x2 293 294 /* Restore ESR_EL3 and SCR_EL3 */ 295 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 296 msr scr_el3, x3 297 msr esr_el3, x4 298 299#if ENABLE_ASSERTIONS 300 cmp x4, xzr 301 ASM_ASSERT(ne) 302#endif 303 304 /* Clear ESR storage */ 305 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 306 307 ret x29 308endfunc ea_proceed 309