1df8f3188SJeenu Viswambharan/* 297215e0fSDaniel Boulby * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3df8f3188SJeenu Viswambharan * 4df8f3188SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 5df8f3188SJeenu Viswambharan */ 6df8f3188SJeenu Viswambharan 7df8f3188SJeenu Viswambharan 8d5a23af5SJeenu Viswambharan#include <assert_macros.S> 9df8f3188SJeenu Viswambharan#include <asm_macros.S> 10ee6ff1bbSJeenu Viswambharan#include <assert_macros.S> 1109d40e0eSAntonio Nino Diaz#include <bl31/ea_handle.h> 12df8f3188SJeenu Viswambharan#include <context.h> 1309d40e0eSAntonio Nino Diaz#include <lib/extensions/ras_arch.h> 1480942622Slaurenw-arm#include <cpu_macros.S> 1580942622Slaurenw-arm#include <context.h> 16df8f3188SJeenu Viswambharan 17df8f3188SJeenu Viswambharan .globl handle_lower_el_ea_esb 18c2d32a5fSMadhukar Pappireddy .globl handle_lower_el_async_ea 19df8f3188SJeenu Viswambharan .globl enter_lower_el_sync_ea 20df8f3188SJeenu Viswambharan .globl enter_lower_el_async_ea 21df8f3188SJeenu Viswambharan 22df8f3188SJeenu Viswambharan 23df8f3188SJeenu Viswambharan/* 24df8f3188SJeenu Viswambharan * Function to delegate External Aborts synchronized by ESB instruction at EL3 25df8f3188SJeenu Viswambharan * vector entry. This function assumes GP registers x0-x29 have been saved, and 26df8f3188SJeenu Viswambharan * are available for use. It delegates the handling of the EA to platform 27df8f3188SJeenu Viswambharan * handler, and returns only upon successfully handling the EA; otherwise 28df8f3188SJeenu Viswambharan * panics. On return from this function, the original exception handler is 29df8f3188SJeenu Viswambharan * expected to resume. 30df8f3188SJeenu Viswambharan */ 31df8f3188SJeenu Viswambharanfunc handle_lower_el_ea_esb 32df8f3188SJeenu Viswambharan mov x0, #ERROR_EA_ESB 33df8f3188SJeenu Viswambharan mrs x1, DISR_EL1 34df8f3188SJeenu Viswambharan b ea_proceed 35df8f3188SJeenu Viswambharanendfunc handle_lower_el_ea_esb 36df8f3188SJeenu Viswambharan 37df8f3188SJeenu Viswambharan 38df8f3188SJeenu Viswambharan/* 39df8f3188SJeenu Viswambharan * This function forms the tail end of Synchronous Exception entry from lower 4080942622Slaurenw-arm * EL, and expects to handle Synchronous External Aborts from lower EL and CPU 4180942622Slaurenw-arm * Implementation Defined Exceptions. If any other kind of exception is detected, 4280942622Slaurenw-arm * then this function reports unhandled exception. 43df8f3188SJeenu Viswambharan * 44df8f3188SJeenu Viswambharan * Since it's part of exception vector, this function doesn't expect any GP 45df8f3188SJeenu Viswambharan * registers to have been saved. It delegates the handling of the EA to platform 46df8f3188SJeenu Viswambharan * handler, and upon successfully handling the EA, exits EL3; otherwise panics. 47df8f3188SJeenu Viswambharan */ 48df8f3188SJeenu Viswambharanfunc enter_lower_el_sync_ea 49df8f3188SJeenu Viswambharan /* 50df8f3188SJeenu Viswambharan * Explicitly save x30 so as to free up a register and to enable 51df8f3188SJeenu Viswambharan * branching. 52df8f3188SJeenu Viswambharan */ 53df8f3188SJeenu Viswambharan str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 54df8f3188SJeenu Viswambharan 55df8f3188SJeenu Viswambharan mrs x30, esr_el3 56df8f3188SJeenu Viswambharan ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 57df8f3188SJeenu Viswambharan 58df8f3188SJeenu Viswambharan /* Check for I/D aborts from lower EL */ 59df8f3188SJeenu Viswambharan cmp x30, #EC_IABORT_LOWER_EL 60df8f3188SJeenu Viswambharan b.eq 1f 61df8f3188SJeenu Viswambharan 62df8f3188SJeenu Viswambharan cmp x30, #EC_DABORT_LOWER_EL 6380942622Slaurenw-arm b.eq 1f 6480942622Slaurenw-arm 6580942622Slaurenw-arm /* Save GP registers */ 6680942622Slaurenw-arm stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 6780942622Slaurenw-arm stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 6880942622Slaurenw-arm stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 6980942622Slaurenw-arm 7080942622Slaurenw-arm /* Get the cpu_ops pointer */ 7180942622Slaurenw-arm bl get_cpu_ops_ptr 7280942622Slaurenw-arm 7380942622Slaurenw-arm /* Get the cpu_ops exception handler */ 7480942622Slaurenw-arm ldr x0, [x0, #CPU_E_HANDLER_FUNC] 7580942622Slaurenw-arm 7680942622Slaurenw-arm /* 7780942622Slaurenw-arm * If the reserved function pointer is NULL, this CPU does not have an 7880942622Slaurenw-arm * implementation defined exception handler function 7980942622Slaurenw-arm */ 8080942622Slaurenw-arm cbz x0, 2f 8180942622Slaurenw-arm mrs x1, esr_el3 8280942622Slaurenw-arm ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH 8380942622Slaurenw-arm blr x0 8480942622Slaurenw-arm b 2f 85df8f3188SJeenu Viswambharan 86df8f3188SJeenu Viswambharan1: 87df8f3188SJeenu Viswambharan /* Test for EA bit in the instruction syndrome */ 88df8f3188SJeenu Viswambharan mrs x30, esr_el3 8980942622Slaurenw-arm tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f 90df8f3188SJeenu Viswambharan 91e290a8fcSAlexei Fedorov /* 92ed108b56SAlexei Fedorov * Save general purpose and ARMv8.3-PAuth registers (if enabled). 93ed108b56SAlexei Fedorov * If Secure Cycle Counter is not disabled in MDCR_EL3 when 94ed108b56SAlexei Fedorov * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 95*7d33ffe4SDaniel Boulby * Also set the PSTATE to a known state. 96e290a8fcSAlexei Fedorov */ 9797215e0fSDaniel Boulby bl prepare_el3_entry 98e290a8fcSAlexei Fedorov 99b86048c4SAntonio Nino Diaz#if ENABLE_PAUTH 100ed108b56SAlexei Fedorov /* Load and program APIAKey firmware key */ 101ed108b56SAlexei Fedorov bl pauth_load_bl31_apiakey 102b86048c4SAntonio Nino Diaz#endif 1035283962eSAntonio Nino Diaz 104df8f3188SJeenu Viswambharan /* Setup exception class and syndrome arguments for platform handler */ 105df8f3188SJeenu Viswambharan mov x0, #ERROR_EA_SYNC 106df8f3188SJeenu Viswambharan mrs x1, esr_el3 107bb9549baSJan Dabros bl delegate_sync_ea 108df8f3188SJeenu Viswambharan 109bb9549baSJan Dabros /* el3_exit assumes SP_EL0 on entry */ 110bb9549baSJan Dabros msr spsel, #MODE_SP_EL0 111bb9549baSJan Dabros b el3_exit 112df8f3188SJeenu Viswambharan2: 11380942622Slaurenw-arm ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 11480942622Slaurenw-arm ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 11580942622Slaurenw-arm ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 11680942622Slaurenw-arm 11780942622Slaurenw-arm3: 118df8f3188SJeenu Viswambharan /* Synchronous exceptions other than the above are assumed to be EA */ 119df8f3188SJeenu Viswambharan ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 120df8f3188SJeenu Viswambharan no_ret report_unhandled_exception 121df8f3188SJeenu Viswambharanendfunc enter_lower_el_sync_ea 122df8f3188SJeenu Viswambharan 123df8f3188SJeenu Viswambharan 124df8f3188SJeenu Viswambharan/* 125df8f3188SJeenu Viswambharan * This function handles SErrors from lower ELs. 126df8f3188SJeenu Viswambharan * 127df8f3188SJeenu Viswambharan * Since it's part of exception vector, this function doesn't expect any GP 128df8f3188SJeenu Viswambharan * registers to have been saved. It delegates the handling of the EA to platform 129df8f3188SJeenu Viswambharan * handler, and upon successfully handling the EA, exits EL3; otherwise panics. 130df8f3188SJeenu Viswambharan */ 131df8f3188SJeenu Viswambharanfunc enter_lower_el_async_ea 132df8f3188SJeenu Viswambharan /* 133df8f3188SJeenu Viswambharan * Explicitly save x30 so as to free up a register and to enable 134df8f3188SJeenu Viswambharan * branching 135df8f3188SJeenu Viswambharan */ 136df8f3188SJeenu Viswambharan str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 137df8f3188SJeenu Viswambharan 138c2d32a5fSMadhukar Pappireddyhandle_lower_el_async_ea: 139e290a8fcSAlexei Fedorov /* 140ed108b56SAlexei Fedorov * Save general purpose and ARMv8.3-PAuth registers (if enabled). 141ed108b56SAlexei Fedorov * If Secure Cycle Counter is not disabled in MDCR_EL3 when 142ed108b56SAlexei Fedorov * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 143*7d33ffe4SDaniel Boulby * Also set the PSTATE to a known state. 144e290a8fcSAlexei Fedorov */ 14597215e0fSDaniel Boulby bl prepare_el3_entry 146e290a8fcSAlexei Fedorov 147b86048c4SAntonio Nino Diaz#if ENABLE_PAUTH 148ed108b56SAlexei Fedorov /* Load and program APIAKey firmware key */ 149ed108b56SAlexei Fedorov bl pauth_load_bl31_apiakey 150b86048c4SAntonio Nino Diaz#endif 1515283962eSAntonio Nino Diaz 152df8f3188SJeenu Viswambharan /* Setup exception class and syndrome arguments for platform handler */ 153df8f3188SJeenu Viswambharan mov x0, #ERROR_EA_ASYNC 154df8f3188SJeenu Viswambharan mrs x1, esr_el3 155bb9549baSJan Dabros bl delegate_async_ea 156bb9549baSJan Dabros 157bb9549baSJan Dabros /* el3_exit assumes SP_EL0 on entry */ 158bb9549baSJan Dabros msr spsel, #MODE_SP_EL0 159bb9549baSJan Dabros b el3_exit 160df8f3188SJeenu Viswambharanendfunc enter_lower_el_async_ea 161df8f3188SJeenu Viswambharan 162df8f3188SJeenu Viswambharan 163df8f3188SJeenu Viswambharan/* 164b56dc2a9SJeenu Viswambharan * Prelude for Synchronous External Abort handling. This function assumes that 165b56dc2a9SJeenu Viswambharan * all GP registers have been saved by the caller. 166b56dc2a9SJeenu Viswambharan * 167b56dc2a9SJeenu Viswambharan * x0: EA reason 168b56dc2a9SJeenu Viswambharan * x1: EA syndrome 169b56dc2a9SJeenu Viswambharan */ 170b56dc2a9SJeenu Viswambharanfunc delegate_sync_ea 171b56dc2a9SJeenu Viswambharan#if RAS_EXTENSION 172b56dc2a9SJeenu Viswambharan /* 173b56dc2a9SJeenu Viswambharan * Check for Uncontainable error type. If so, route to the platform 174b56dc2a9SJeenu Viswambharan * fatal error handler rather than the generic EA one. 175b56dc2a9SJeenu Viswambharan */ 176b56dc2a9SJeenu Viswambharan ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH 177b56dc2a9SJeenu Viswambharan cmp x2, #ERROR_STATUS_SET_UC 178b56dc2a9SJeenu Viswambharan b.ne 1f 179b56dc2a9SJeenu Viswambharan 180b56dc2a9SJeenu Viswambharan /* Check fault status code */ 181b56dc2a9SJeenu Viswambharan ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 182b56dc2a9SJeenu Viswambharan cmp x3, #SYNC_EA_FSC 183b56dc2a9SJeenu Viswambharan b.ne 1f 184b56dc2a9SJeenu Viswambharan 185b56dc2a9SJeenu Viswambharan no_ret plat_handle_uncontainable_ea 186b56dc2a9SJeenu Viswambharan1: 187b56dc2a9SJeenu Viswambharan#endif 188b56dc2a9SJeenu Viswambharan 189b56dc2a9SJeenu Viswambharan b ea_proceed 190b56dc2a9SJeenu Viswambharanendfunc delegate_sync_ea 191b56dc2a9SJeenu Viswambharan 192b56dc2a9SJeenu Viswambharan 193b56dc2a9SJeenu Viswambharan/* 194b56dc2a9SJeenu Viswambharan * Prelude for Asynchronous External Abort handling. This function assumes that 195b56dc2a9SJeenu Viswambharan * all GP registers have been saved by the caller. 196b56dc2a9SJeenu Viswambharan * 197b56dc2a9SJeenu Viswambharan * x0: EA reason 198b56dc2a9SJeenu Viswambharan * x1: EA syndrome 199b56dc2a9SJeenu Viswambharan */ 200b56dc2a9SJeenu Viswambharanfunc delegate_async_ea 201b56dc2a9SJeenu Viswambharan#if RAS_EXTENSION 202b56dc2a9SJeenu Viswambharan /* 203b56dc2a9SJeenu Viswambharan * Check for Implementation Defined Syndrome. If so, skip checking 204b56dc2a9SJeenu Viswambharan * Uncontainable error type from the syndrome as the format is unknown. 205b56dc2a9SJeenu Viswambharan */ 206b56dc2a9SJeenu Viswambharan tbnz x1, #SERROR_IDS_BIT, 1f 207b56dc2a9SJeenu Viswambharan 208b56dc2a9SJeenu Viswambharan /* 209b56dc2a9SJeenu Viswambharan * Check for Uncontainable error type. If so, route to the platform 210b56dc2a9SJeenu Viswambharan * fatal error handler rather than the generic EA one. 211b56dc2a9SJeenu Viswambharan */ 212b56dc2a9SJeenu Viswambharan ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH 213b56dc2a9SJeenu Viswambharan cmp x2, #ERROR_STATUS_UET_UC 214b56dc2a9SJeenu Viswambharan b.ne 1f 215b56dc2a9SJeenu Viswambharan 216b56dc2a9SJeenu Viswambharan /* Check DFSC for SError type */ 217b56dc2a9SJeenu Viswambharan ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH 218b56dc2a9SJeenu Viswambharan cmp x3, #DFSC_SERROR 219b56dc2a9SJeenu Viswambharan b.ne 1f 220b56dc2a9SJeenu Viswambharan 221b56dc2a9SJeenu Viswambharan no_ret plat_handle_uncontainable_ea 222b56dc2a9SJeenu Viswambharan1: 223b56dc2a9SJeenu Viswambharan#endif 224b56dc2a9SJeenu Viswambharan 225b56dc2a9SJeenu Viswambharan b ea_proceed 226b56dc2a9SJeenu Viswambharanendfunc delegate_async_ea 227b56dc2a9SJeenu Viswambharan 228b56dc2a9SJeenu Viswambharan 229b56dc2a9SJeenu Viswambharan/* 230df8f3188SJeenu Viswambharan * Delegate External Abort handling to platform's EA handler. This function 231df8f3188SJeenu Viswambharan * assumes that all GP registers have been saved by the caller. 232df8f3188SJeenu Viswambharan * 233df8f3188SJeenu Viswambharan * x0: EA reason 234df8f3188SJeenu Viswambharan * x1: EA syndrome 235df8f3188SJeenu Viswambharan */ 236df8f3188SJeenu Viswambharanfunc ea_proceed 237d5a23af5SJeenu Viswambharan /* 238d5a23af5SJeenu Viswambharan * If the ESR loaded earlier is not zero, we were processing an EA 239d5a23af5SJeenu Viswambharan * already, and this is a double fault. 240d5a23af5SJeenu Viswambharan */ 241d5a23af5SJeenu Viswambharan ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 242d5a23af5SJeenu Viswambharan cbz x5, 1f 243d5a23af5SJeenu Viswambharan no_ret plat_handle_double_fault 244d5a23af5SJeenu Viswambharan 245d5a23af5SJeenu Viswambharan1: 246df8f3188SJeenu Viswambharan /* Save EL3 state */ 247df8f3188SJeenu Viswambharan mrs x2, spsr_el3 248df8f3188SJeenu Viswambharan mrs x3, elr_el3 249df8f3188SJeenu Viswambharan stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 250df8f3188SJeenu Viswambharan 251df8f3188SJeenu Viswambharan /* 252df8f3188SJeenu Viswambharan * Save ESR as handling might involve lower ELs, and returning back to 253df8f3188SJeenu Viswambharan * EL3 from there would trample the original ESR. 254df8f3188SJeenu Viswambharan */ 255df8f3188SJeenu Viswambharan mrs x4, scr_el3 256df8f3188SJeenu Viswambharan mrs x5, esr_el3 257df8f3188SJeenu Viswambharan stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 258df8f3188SJeenu Viswambharan 259df8f3188SJeenu Viswambharan /* 260df8f3188SJeenu Viswambharan * Setup rest of arguments, and call platform External Abort handler. 261df8f3188SJeenu Viswambharan * 262df8f3188SJeenu Viswambharan * x0: EA reason (already in place) 263df8f3188SJeenu Viswambharan * x1: Exception syndrome (already in place). 264df8f3188SJeenu Viswambharan * x2: Cookie (unused for now). 265df8f3188SJeenu Viswambharan * x3: Context pointer. 266df8f3188SJeenu Viswambharan * x4: Flags (security state from SCR for now). 267df8f3188SJeenu Viswambharan */ 268df8f3188SJeenu Viswambharan mov x2, xzr 269df8f3188SJeenu Viswambharan mov x3, sp 270df8f3188SJeenu Viswambharan ubfx x4, x4, #0, #1 271df8f3188SJeenu Viswambharan 272df8f3188SJeenu Viswambharan /* Switch to runtime stack */ 273df8f3188SJeenu Viswambharan ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 274ed108b56SAlexei Fedorov msr spsel, #MODE_SP_EL0 275df8f3188SJeenu Viswambharan mov sp, x5 276df8f3188SJeenu Viswambharan 277df8f3188SJeenu Viswambharan mov x29, x30 278ee6ff1bbSJeenu Viswambharan#if ENABLE_ASSERTIONS 279ee6ff1bbSJeenu Viswambharan /* Stash the stack pointer */ 280ee6ff1bbSJeenu Viswambharan mov x28, sp 281ee6ff1bbSJeenu Viswambharan#endif 282df8f3188SJeenu Viswambharan bl plat_ea_handler 283df8f3188SJeenu Viswambharan 284ee6ff1bbSJeenu Viswambharan#if ENABLE_ASSERTIONS 285ee6ff1bbSJeenu Viswambharan /* 286ee6ff1bbSJeenu Viswambharan * Error handling flows might involve long jumps; so upon returning from 287ee6ff1bbSJeenu Viswambharan * the platform error handler, validate that the we've completely 288ee6ff1bbSJeenu Viswambharan * unwound the stack. 289ee6ff1bbSJeenu Viswambharan */ 290ee6ff1bbSJeenu Viswambharan mov x27, sp 291ee6ff1bbSJeenu Viswambharan cmp x28, x27 292ee6ff1bbSJeenu Viswambharan ASM_ASSERT(eq) 293ee6ff1bbSJeenu Viswambharan#endif 294ee6ff1bbSJeenu Viswambharan 295df8f3188SJeenu Viswambharan /* Make SP point to context */ 296ed108b56SAlexei Fedorov msr spsel, #MODE_SP_ELX 297df8f3188SJeenu Viswambharan 298d5a23af5SJeenu Viswambharan /* Restore EL3 state and ESR */ 299df8f3188SJeenu Viswambharan ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 300df8f3188SJeenu Viswambharan msr spsr_el3, x1 301df8f3188SJeenu Viswambharan msr elr_el3, x2 302df8f3188SJeenu Viswambharan 303df8f3188SJeenu Viswambharan /* Restore ESR_EL3 and SCR_EL3 */ 304df8f3188SJeenu Viswambharan ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 305df8f3188SJeenu Viswambharan msr scr_el3, x3 306df8f3188SJeenu Viswambharan msr esr_el3, x4 307df8f3188SJeenu Viswambharan 308d5a23af5SJeenu Viswambharan#if ENABLE_ASSERTIONS 309d5a23af5SJeenu Viswambharan cmp x4, xzr 310d5a23af5SJeenu Viswambharan ASM_ASSERT(ne) 311d5a23af5SJeenu Viswambharan#endif 312d5a23af5SJeenu Viswambharan 313d5a23af5SJeenu Viswambharan /* Clear ESR storage */ 314d5a23af5SJeenu Viswambharan str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] 315d5a23af5SJeenu Viswambharan 316d5a23af5SJeenu Viswambharan ret x29 317df8f3188SJeenu Viswambharanendfunc ea_proceed 318