xref: /rk3399_ARM-atf/bl31/aarch64/crash_reporting.S (revision 9c22b32300320c40aa36f73f84a51cdc5218780e)
1a43d431bSSoby Mathew/*
2a43d431bSSoby Mathew * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3a43d431bSSoby Mathew *
4a43d431bSSoby Mathew * Redistribution and use in source and binary forms, with or without
5a43d431bSSoby Mathew * modification, are permitted provided that the following conditions are met:
6a43d431bSSoby Mathew *
7a43d431bSSoby Mathew * Redistributions of source code must retain the above copyright notice, this
8a43d431bSSoby Mathew * list of conditions and the following disclaimer.
9a43d431bSSoby Mathew *
10a43d431bSSoby Mathew * Redistributions in binary form must reproduce the above copyright notice,
11a43d431bSSoby Mathew * this list of conditions and the following disclaimer in the documentation
12a43d431bSSoby Mathew * and/or other materials provided with the distribution.
13a43d431bSSoby Mathew *
14a43d431bSSoby Mathew * Neither the name of ARM nor the names of its contributors may be used
15a43d431bSSoby Mathew * to endorse or promote products derived from this software without specific
16a43d431bSSoby Mathew * prior written permission.
17a43d431bSSoby Mathew *
18a43d431bSSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19a43d431bSSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20a43d431bSSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21a43d431bSSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22a43d431bSSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23a43d431bSSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24a43d431bSSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25a43d431bSSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26a43d431bSSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27a43d431bSSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28a43d431bSSoby Mathew * POSSIBILITY OF SUCH DAMAGE.
29a43d431bSSoby Mathew */
30a43d431bSSoby Mathew#include <arch.h>
31a43d431bSSoby Mathew#include <asm_macros.S>
32a43d431bSSoby Mathew#include <context.h>
33a43d431bSSoby Mathew#include <plat_macros.S>
34a43d431bSSoby Mathew
35a43d431bSSoby Mathew	.globl	get_crash_stack
36a43d431bSSoby Mathew	.globl	dump_state_and_die
37a43d431bSSoby Mathew	.globl	dump_intr_state_and_die
38a43d431bSSoby Mathew
39*9c22b323SAndrew Thoelke#if CRASH_REPORTING
40a43d431bSSoby Mathew	/* ------------------------------------------------------
41a43d431bSSoby Mathew	 * The below section deals with dumping the system state
42a43d431bSSoby Mathew	 * when an unhandled exception is taken in EL3.
43a43d431bSSoby Mathew	 * The layout and the names of the registers which will
44a43d431bSSoby Mathew	 * be dumped during a unhandled exception is given below.
45a43d431bSSoby Mathew	 * ------------------------------------------------------
46a43d431bSSoby Mathew	 */
47a43d431bSSoby Mathew.section .rodata.dump_reg_name, "aS"
48a43d431bSSoby Mathewcaller_saved_regs:	.asciz	"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
49a43d431bSSoby Mathew	 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16",\
50a43d431bSSoby Mathew	 "x17", "x18", ""
51a43d431bSSoby Mathew
52a43d431bSSoby Mathewcallee_saved_regs: .asciz	"x19", "x20", "x21", "x22", "x23", "x24",\
53a43d431bSSoby Mathew	 "x25", "x26", "x27", "x28", "x29", "x30", ""
54a43d431bSSoby Mathew
55a43d431bSSoby Mathewel3_sys_regs: .asciz	"scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\
56a43d431bSSoby Mathew	 "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3", "esr_el3",\
57a43d431bSSoby Mathew	 "sp_el3", "far_el3", ""
58a43d431bSSoby Mathew
59a43d431bSSoby Mathewnon_el3_sys_0_regs: .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\
60a43d431bSSoby Mathew	"spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\
61a43d431bSSoby Mathew	"csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\
62a43d431bSSoby Mathew	"mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", ""
63a43d431bSSoby Mathew
64a43d431bSSoby Mathewnon_el3_sys_1_regs: .asciz "tpidr_el0", "tpidrro_el0", "dacr32_el2",\
65a43d431bSSoby Mathew	"ifsr32_el2", "par_el1", "far_el1", "afsr0_el1", "afsr1_el1",\
66a43d431bSSoby Mathew	"contextidr_el1", "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0",\
67a43d431bSSoby Mathew	"cntv_ctl_el0", "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2",\
68a43d431bSSoby Mathew	"sp_el0", ""
69a43d431bSSoby Mathew
70a43d431bSSoby Mathew	/* -----------------------------------------------------
71a43d431bSSoby Mathew	 * Currently we are stack limited. Hence make sure that
72a43d431bSSoby Mathew	 * we dont try to dump more than 20 registers using the
73a43d431bSSoby Mathew	 * stack.
74a43d431bSSoby Mathew	 * -----------------------------------------------------
75a43d431bSSoby Mathew	 */
76a43d431bSSoby Mathew
77a43d431bSSoby Mathew#define REG_SIZE 0x8
78a43d431bSSoby Mathew
79a43d431bSSoby Mathew/* The caller saved registers are X0 to X18 */
80a43d431bSSoby Mathew#define CALLER_SAVED_REG_SIZE 		(20 * REG_SIZE)
81a43d431bSSoby Mathew/* The caller saved registers are X19 to X30 */
82a43d431bSSoby Mathew#define CALLEE_SAVED_REG_SIZE 		(12 * REG_SIZE)
83a43d431bSSoby Mathew/* The EL3 sys regs*/
84a43d431bSSoby Mathew#define EL3_SYS_REG_SIZE 			(12 * REG_SIZE)
85a43d431bSSoby Mathew/* The non EL3 sys regs set-0 */
86a43d431bSSoby Mathew#define NON_EL3_SYS_0_REG_SIZE 		(18 * REG_SIZE)
87a43d431bSSoby Mathew/* The non EL3 sys regs set-1 */
88a43d431bSSoby Mathew#define NON_EL3_SYS_1_REG_SIZE 		(18 * REG_SIZE)
89a43d431bSSoby Mathew
90a43d431bSSoby Mathew	.macro print_caller_saved_regs
91a43d431bSSoby Mathew	sub	sp, sp, #CALLER_SAVED_REG_SIZE
92a43d431bSSoby Mathew	stp	x0, x1, [sp]
93a43d431bSSoby Mathew	stp	x2, x3, [sp, #(REG_SIZE * 2)]
94a43d431bSSoby Mathew	stp	x4, x5, [sp, #(REG_SIZE * 4)]
95a43d431bSSoby Mathew	stp	x6, x7, [sp, #(REG_SIZE * 6)]
96a43d431bSSoby Mathew	stp	x8, x9, [sp, #(REG_SIZE * 8)]
97a43d431bSSoby Mathew	stp	x10, x11, [sp, #(REG_SIZE * 10)]
98a43d431bSSoby Mathew	stp	x12, x13, [sp, #(REG_SIZE * 12)]
99a43d431bSSoby Mathew	stp	x14, x15, [sp, #(REG_SIZE * 14)]
100a43d431bSSoby Mathew	stp	x16, x17, [sp, #(REG_SIZE * 16)]
101a43d431bSSoby Mathew	stp	x18, xzr, [sp, #(REG_SIZE * 18)]
102a43d431bSSoby Mathew	adr	x0, caller_saved_regs
103a43d431bSSoby Mathew	mov	x1, sp
104a43d431bSSoby Mathew	bl	print_string_value
105a43d431bSSoby Mathew	add	sp, sp, #CALLER_SAVED_REG_SIZE
106a43d431bSSoby Mathew	.endm
107a43d431bSSoby Mathew
108a43d431bSSoby Mathew	.macro print_callee_saved_regs
109a43d431bSSoby Mathew	sub	sp, sp, CALLEE_SAVED_REG_SIZE
110a43d431bSSoby Mathew	stp	x19, x20, [sp]
111a43d431bSSoby Mathew	stp	x21, x22, [sp, #(REG_SIZE * 2)]
112a43d431bSSoby Mathew	stp	x23, x24, [sp, #(REG_SIZE * 4)]
113a43d431bSSoby Mathew	stp	x25, x26, [sp, #(REG_SIZE * 6)]
114a43d431bSSoby Mathew	stp	x27, x28, [sp, #(REG_SIZE * 8)]
115a43d431bSSoby Mathew	stp	x29, x30, [sp, #(REG_SIZE * 10)]
116a43d431bSSoby Mathew	adr	x0, callee_saved_regs
117a43d431bSSoby Mathew	mov	x1, sp
118a43d431bSSoby Mathew	bl	print_string_value
119a43d431bSSoby Mathew	add	sp, sp, #CALLEE_SAVED_REG_SIZE
120a43d431bSSoby Mathew	.endm
121a43d431bSSoby Mathew
122a43d431bSSoby Mathew	.macro print_el3_sys_regs
123a43d431bSSoby Mathew	sub	sp, sp, #EL3_SYS_REG_SIZE
124a43d431bSSoby Mathew	mrs	x9, scr_el3
125a43d431bSSoby Mathew	mrs	x10, sctlr_el3
126a43d431bSSoby Mathew	mrs	x11, cptr_el3
127a43d431bSSoby Mathew	mrs	x12, tcr_el3
128a43d431bSSoby Mathew	mrs	x13, daif
129a43d431bSSoby Mathew	mrs	x14, mair_el3
130a43d431bSSoby Mathew	mrs	x15, spsr_el3 /*save the elr and spsr regs seperately*/
131a43d431bSSoby Mathew	mrs	x16, elr_el3
132a43d431bSSoby Mathew	mrs	x17, ttbr0_el3
133a43d431bSSoby Mathew	mrs	x8, esr_el3
134a43d431bSSoby Mathew	mrs	x7, far_el3
135a43d431bSSoby Mathew
136a43d431bSSoby Mathew	stp	x9, x10, [sp]
137a43d431bSSoby Mathew	stp	x11, x12, [sp, #(REG_SIZE * 2)]
138a43d431bSSoby Mathew	stp	x13, x14, [sp, #(REG_SIZE * 4)]
139a43d431bSSoby Mathew	stp	x15, x16, [sp, #(REG_SIZE * 6)]
140a43d431bSSoby Mathew	stp	x17, x8, [sp, #(REG_SIZE * 8)]
141a43d431bSSoby Mathew	stp	x0, x7, [sp, #(REG_SIZE * 10)] /* sp_el3 is in x0 */
142a43d431bSSoby Mathew
143a43d431bSSoby Mathew	adr	x0, el3_sys_regs
144a43d431bSSoby Mathew	mov	x1, sp
145a43d431bSSoby Mathew	bl	print_string_value
146a43d431bSSoby Mathew	add	sp, sp, #EL3_SYS_REG_SIZE
147a43d431bSSoby Mathew	.endm
148a43d431bSSoby Mathew
149a43d431bSSoby Mathew	.macro print_non_el3_sys_0_regs
150a43d431bSSoby Mathew	sub	sp, sp, #NON_EL3_SYS_0_REG_SIZE
151a43d431bSSoby Mathew	mrs	x9, spsr_el1
152a43d431bSSoby Mathew	mrs	x10, elr_el1
153a43d431bSSoby Mathew	mrs	x11, spsr_abt
154a43d431bSSoby Mathew	mrs	x12, spsr_und
155a43d431bSSoby Mathew	mrs	x13, spsr_irq
156a43d431bSSoby Mathew	mrs	x14, spsr_fiq
157a43d431bSSoby Mathew	mrs	x15, sctlr_el1
158a43d431bSSoby Mathew	mrs	x16, actlr_el1
159a43d431bSSoby Mathew	mrs	x17, cpacr_el1
160a43d431bSSoby Mathew	mrs	x8, csselr_el1
161a43d431bSSoby Mathew
162a43d431bSSoby Mathew	stp	x9, x10, [sp]
163a43d431bSSoby Mathew	stp	x11, x12, [sp, #(REG_SIZE * 2)]
164a43d431bSSoby Mathew	stp	x13, x14, [sp, #(REG_SIZE * 4)]
165a43d431bSSoby Mathew	stp	x15, x16, [sp, #(REG_SIZE * 6)]
166a43d431bSSoby Mathew	stp	x17, x8, [sp, #(REG_SIZE * 8)]
167a43d431bSSoby Mathew
168a43d431bSSoby Mathew	mrs	x10, sp_el1
169a43d431bSSoby Mathew	mrs	x11, esr_el1
170a43d431bSSoby Mathew	mrs	x12, ttbr0_el1
171a43d431bSSoby Mathew	mrs	x13, ttbr1_el1
172a43d431bSSoby Mathew	mrs	x14, mair_el1
173a43d431bSSoby Mathew	mrs	x15, amair_el1
174a43d431bSSoby Mathew	mrs	x16, tcr_el1
175a43d431bSSoby Mathew	mrs	x17, tpidr_el1
176a43d431bSSoby Mathew
177a43d431bSSoby Mathew	stp	x10, x11, [sp, #(REG_SIZE * 10)]
178a43d431bSSoby Mathew	stp	x12, x13, [sp, #(REG_SIZE * 12)]
179a43d431bSSoby Mathew	stp	x14, x15, [sp, #(REG_SIZE * 14)]
180a43d431bSSoby Mathew	stp	x16, x17, [sp, #(REG_SIZE * 16)]
181a43d431bSSoby Mathew
182a43d431bSSoby Mathew	adr	x0, non_el3_sys_0_regs
183a43d431bSSoby Mathew	mov	x1, sp
184a43d431bSSoby Mathew	bl	print_string_value
185a43d431bSSoby Mathew	add	sp, sp, #NON_EL3_SYS_0_REG_SIZE
186a43d431bSSoby Mathew	.endm
187a43d431bSSoby Mathew
188a43d431bSSoby Mathew	.macro print_non_el3_sys_1_regs
189a43d431bSSoby Mathew	sub	sp, sp, #NON_EL3_SYS_1_REG_SIZE
190a43d431bSSoby Mathew
191a43d431bSSoby Mathew	mrs	x9, tpidr_el0
192a43d431bSSoby Mathew	mrs	x10, tpidrro_el0
193a43d431bSSoby Mathew	mrs	x11, dacr32_el2
194a43d431bSSoby Mathew	mrs	x12, ifsr32_el2
195a43d431bSSoby Mathew	mrs	x13, par_el1
196a43d431bSSoby Mathew	mrs	x14, far_el1
197a43d431bSSoby Mathew	mrs	x15, afsr0_el1
198a43d431bSSoby Mathew	mrs	x16, afsr1_el1
199a43d431bSSoby Mathew	mrs	x17, contextidr_el1
200a43d431bSSoby Mathew	mrs	x8, vbar_el1
201a43d431bSSoby Mathew
202a43d431bSSoby Mathew	stp	x9, x10, [sp]
203a43d431bSSoby Mathew	stp	x11, x12, [sp, #(REG_SIZE * 2)]
204a43d431bSSoby Mathew	stp	x13, x14, [sp, #(REG_SIZE * 4)]
205a43d431bSSoby Mathew	stp	x15, x16, [sp, #(REG_SIZE * 6)]
206a43d431bSSoby Mathew	stp	x17, x8, [sp, #(REG_SIZE * 8)]
207a43d431bSSoby Mathew
208a43d431bSSoby Mathew	mrs	x10, cntp_ctl_el0
209a43d431bSSoby Mathew	mrs	x11, cntp_cval_el0
210a43d431bSSoby Mathew	mrs	x12, cntv_ctl_el0
211a43d431bSSoby Mathew	mrs	x13, cntv_cval_el0
212a43d431bSSoby Mathew	mrs	x14, cntkctl_el1
213a43d431bSSoby Mathew	mrs	x15, fpexc32_el2
214a43d431bSSoby Mathew	mrs	x8, sp_el0
215a43d431bSSoby Mathew
216a43d431bSSoby Mathew	stp	x10, x11, [sp, #(REG_SIZE *10)]
217a43d431bSSoby Mathew	stp	x12, x13, [sp, #(REG_SIZE * 12)]
218a43d431bSSoby Mathew	stp	x14, x15, [sp, #(REG_SIZE * 14)]
219a43d431bSSoby Mathew	stp	x8, xzr, [sp, #(REG_SIZE * 16)]
220a43d431bSSoby Mathew
221a43d431bSSoby Mathew	adr	x0, non_el3_sys_1_regs
222a43d431bSSoby Mathew	mov	x1, sp
223a43d431bSSoby Mathew	bl	print_string_value
224a43d431bSSoby Mathew	add	sp, sp, #NON_EL3_SYS_1_REG_SIZE
225a43d431bSSoby Mathew	.endm
226a43d431bSSoby Mathew
227a43d431bSSoby Mathew	.macro init_crash_stack
228a43d431bSSoby Mathew	msr	cntfrq_el0, x0 /* we can corrupt this reg to free up x0 */
229a43d431bSSoby Mathew	mrs	x0, tpidr_el3
230a43d431bSSoby Mathew
231a43d431bSSoby Mathew	/* Check if tpidr is initialized */
232a43d431bSSoby Mathew	cbz	x0, infinite_loop
233a43d431bSSoby Mathew
234a43d431bSSoby Mathew	ldr	x0, [x0, #PTR_CACHE_CRASH_STACK_OFFSET]
235a43d431bSSoby Mathew	/* store the x30 and sp to stack */
236a43d431bSSoby Mathew	str	x30, [x0, #-(REG_SIZE)]!
237a43d431bSSoby Mathew	mov	x30, sp
238a43d431bSSoby Mathew	str	x30, [x0, #-(REG_SIZE)]!
239a43d431bSSoby Mathew	mov	sp, x0
240a43d431bSSoby Mathew	mrs	x0, cntfrq_el0
241a43d431bSSoby Mathew	.endm
242a43d431bSSoby Mathew
243a43d431bSSoby Mathew	/* ---------------------------------------------------
244a43d431bSSoby Mathew	 * The below function initializes the crash dump stack ,
245a43d431bSSoby Mathew	 * and prints the system state. This function
246a43d431bSSoby Mathew	 * will not return.
247a43d431bSSoby Mathew	 * ---------------------------------------------------
248a43d431bSSoby Mathew	 */
249a43d431bSSoby Mathewfunc dump_state_and_die
250a43d431bSSoby Mathew	init_crash_stack
251a43d431bSSoby Mathew	print_caller_saved_regs
252a43d431bSSoby Mathew	b	print_state
253a43d431bSSoby Mathew
254a43d431bSSoby Mathewfunc dump_intr_state_and_die
255a43d431bSSoby Mathew	init_crash_stack
256a43d431bSSoby Mathew	print_caller_saved_regs
257a43d431bSSoby Mathew	plat_print_gic_regs /* fall through to print_state */
258a43d431bSSoby Mathew
259a43d431bSSoby Mathewprint_state:
260a43d431bSSoby Mathew	/* copy the original x30 from stack */
261a43d431bSSoby Mathew	ldr	x30, [sp, #REG_SIZE]
262a43d431bSSoby Mathew	print_callee_saved_regs
263a43d431bSSoby Mathew	/* copy the original SP_EL3 from stack to x0 and rewind stack */
264a43d431bSSoby Mathew	ldr x0, [sp], #(REG_SIZE * 2)
265a43d431bSSoby Mathew	print_el3_sys_regs
266a43d431bSSoby Mathew	print_non_el3_sys_0_regs
267a43d431bSSoby Mathew	print_non_el3_sys_1_regs
268a43d431bSSoby Mathew
269*9c22b323SAndrew Thoelke#else	/* CRASH_REPORING */
270*9c22b323SAndrew Thoelke
271*9c22b323SAndrew Thoelkefunc dump_state_and_die
272*9c22b323SAndrew Thoelkedump_intr_state_and_die:
273*9c22b323SAndrew Thoelke
274*9c22b323SAndrew Thoelke#endif	/* CRASH_REPORING */
275*9c22b323SAndrew Thoelke
276*9c22b323SAndrew Thoelkeinfinite_loop:
277a43d431bSSoby Mathew	b	infinite_loop
278a43d431bSSoby Mathew
279a43d431bSSoby Mathew
280a43d431bSSoby Mathew#define PCPU_CRASH_STACK_SIZE	0x140
281a43d431bSSoby Mathew
282a43d431bSSoby Mathew	/* -----------------------------------------------------
283a43d431bSSoby Mathew	 * void get_crash_stack (uint64_t mpidr) : This
284a43d431bSSoby Mathew	 * function is used to allocate a small stack for
285a43d431bSSoby Mathew	 * reporting unhandled exceptions
286a43d431bSSoby Mathew	 * -----------------------------------------------------
287a43d431bSSoby Mathew	 */
288a43d431bSSoby Mathewfunc get_crash_stack
289a43d431bSSoby Mathew	mov	x10, x30 // lr
290a43d431bSSoby Mathew	get_mp_stack pcpu_crash_stack, PCPU_CRASH_STACK_SIZE
291a43d431bSSoby Mathew	ret	x10
292a43d431bSSoby Mathew
293a43d431bSSoby Mathew	/* -----------------------------------------------------
294a43d431bSSoby Mathew	 * Per-cpu crash stacks in normal memory.
295a43d431bSSoby Mathew	 * -----------------------------------------------------
296a43d431bSSoby Mathew	 */
297a43d431bSSoby Mathewdeclare_stack pcpu_crash_stack, tzfw_normal_stacks, \
298a43d431bSSoby Mathew		PCPU_CRASH_STACK_SIZE, PLATFORM_CORE_COUNT
299