1a43d431bSSoby Mathew/* 2a43d431bSSoby Mathew * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3a43d431bSSoby Mathew * 4a43d431bSSoby Mathew * Redistribution and use in source and binary forms, with or without 5a43d431bSSoby Mathew * modification, are permitted provided that the following conditions are met: 6a43d431bSSoby Mathew * 7a43d431bSSoby Mathew * Redistributions of source code must retain the above copyright notice, this 8a43d431bSSoby Mathew * list of conditions and the following disclaimer. 9a43d431bSSoby Mathew * 10a43d431bSSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 11a43d431bSSoby Mathew * this list of conditions and the following disclaimer in the documentation 12a43d431bSSoby Mathew * and/or other materials provided with the distribution. 13a43d431bSSoby Mathew * 14a43d431bSSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 15a43d431bSSoby Mathew * to endorse or promote products derived from this software without specific 16a43d431bSSoby Mathew * prior written permission. 17a43d431bSSoby Mathew * 18a43d431bSSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19a43d431bSSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20a43d431bSSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21a43d431bSSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22a43d431bSSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23a43d431bSSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24a43d431bSSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25a43d431bSSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26a43d431bSSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27a43d431bSSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28a43d431bSSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 29a43d431bSSoby Mathew */ 30a43d431bSSoby Mathew#include <arch.h> 31a43d431bSSoby Mathew#include <asm_macros.S> 32a43d431bSSoby Mathew#include <context.h> 33*5e910074SAndrew Thoelke#include <cpu_data.h> 34a43d431bSSoby Mathew#include <plat_macros.S> 35e4d13389SSandrine Bailleux#include <platform_def.h> 36a43d431bSSoby Mathew 37a43d431bSSoby Mathew .globl dump_state_and_die 38a43d431bSSoby Mathew .globl dump_intr_state_and_die 39*5e910074SAndrew Thoelke .globl init_crash_reporting 40a43d431bSSoby Mathew 419c22b323SAndrew Thoelke#if CRASH_REPORTING 42a43d431bSSoby Mathew /* ------------------------------------------------------ 43a43d431bSSoby Mathew * The below section deals with dumping the system state 44a43d431bSSoby Mathew * when an unhandled exception is taken in EL3. 45a43d431bSSoby Mathew * The layout and the names of the registers which will 46a43d431bSSoby Mathew * be dumped during a unhandled exception is given below. 47a43d431bSSoby Mathew * ------------------------------------------------------ 48a43d431bSSoby Mathew */ 49a43d431bSSoby Mathew.section .rodata.dump_reg_name, "aS" 50a43d431bSSoby Mathewcaller_saved_regs: .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ 51a43d431bSSoby Mathew "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16",\ 52a43d431bSSoby Mathew "x17", "x18", "" 53a43d431bSSoby Mathew 54a43d431bSSoby Mathewcallee_saved_regs: .asciz "x19", "x20", "x21", "x22", "x23", "x24",\ 55a43d431bSSoby Mathew "x25", "x26", "x27", "x28", "x29", "x30", "" 56a43d431bSSoby Mathew 57a43d431bSSoby Mathewel3_sys_regs: .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ 58a43d431bSSoby Mathew "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3", "esr_el3",\ 59a43d431bSSoby Mathew "sp_el3", "far_el3", "" 60a43d431bSSoby Mathew 61a43d431bSSoby Mathewnon_el3_sys_0_regs: .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\ 62a43d431bSSoby Mathew "spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\ 63a43d431bSSoby Mathew "csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\ 64a43d431bSSoby Mathew "mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "" 65a43d431bSSoby Mathew 66a43d431bSSoby Mathewnon_el3_sys_1_regs: .asciz "tpidr_el0", "tpidrro_el0", "dacr32_el2",\ 67a43d431bSSoby Mathew "ifsr32_el2", "par_el1", "far_el1", "afsr0_el1", "afsr1_el1",\ 68a43d431bSSoby Mathew "contextidr_el1", "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0",\ 69a43d431bSSoby Mathew "cntv_ctl_el0", "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2",\ 70a43d431bSSoby Mathew "sp_el0", "" 71a43d431bSSoby Mathew 72a43d431bSSoby Mathew /* ----------------------------------------------------- 73a43d431bSSoby Mathew * Currently we are stack limited. Hence make sure that 74a43d431bSSoby Mathew * we dont try to dump more than 20 registers using the 75a43d431bSSoby Mathew * stack. 76a43d431bSSoby Mathew * ----------------------------------------------------- 77a43d431bSSoby Mathew */ 78a43d431bSSoby Mathew 79a43d431bSSoby Mathew#define REG_SIZE 0x8 80a43d431bSSoby Mathew 81a43d431bSSoby Mathew/* The caller saved registers are X0 to X18 */ 82a43d431bSSoby Mathew#define CALLER_SAVED_REG_SIZE (20 * REG_SIZE) 83a43d431bSSoby Mathew/* The caller saved registers are X19 to X30 */ 84a43d431bSSoby Mathew#define CALLEE_SAVED_REG_SIZE (12 * REG_SIZE) 85a43d431bSSoby Mathew/* The EL3 sys regs*/ 86a43d431bSSoby Mathew#define EL3_SYS_REG_SIZE (12 * REG_SIZE) 87a43d431bSSoby Mathew/* The non EL3 sys regs set-0 */ 88a43d431bSSoby Mathew#define NON_EL3_SYS_0_REG_SIZE (18 * REG_SIZE) 89a43d431bSSoby Mathew/* The non EL3 sys regs set-1 */ 90a43d431bSSoby Mathew#define NON_EL3_SYS_1_REG_SIZE (18 * REG_SIZE) 91a43d431bSSoby Mathew 92a43d431bSSoby Mathew .macro print_caller_saved_regs 93a43d431bSSoby Mathew sub sp, sp, #CALLER_SAVED_REG_SIZE 94a43d431bSSoby Mathew stp x0, x1, [sp] 95a43d431bSSoby Mathew stp x2, x3, [sp, #(REG_SIZE * 2)] 96a43d431bSSoby Mathew stp x4, x5, [sp, #(REG_SIZE * 4)] 97a43d431bSSoby Mathew stp x6, x7, [sp, #(REG_SIZE * 6)] 98a43d431bSSoby Mathew stp x8, x9, [sp, #(REG_SIZE * 8)] 99a43d431bSSoby Mathew stp x10, x11, [sp, #(REG_SIZE * 10)] 100a43d431bSSoby Mathew stp x12, x13, [sp, #(REG_SIZE * 12)] 101a43d431bSSoby Mathew stp x14, x15, [sp, #(REG_SIZE * 14)] 102a43d431bSSoby Mathew stp x16, x17, [sp, #(REG_SIZE * 16)] 103a43d431bSSoby Mathew stp x18, xzr, [sp, #(REG_SIZE * 18)] 104a43d431bSSoby Mathew adr x0, caller_saved_regs 105a43d431bSSoby Mathew mov x1, sp 106a43d431bSSoby Mathew bl print_string_value 107a43d431bSSoby Mathew add sp, sp, #CALLER_SAVED_REG_SIZE 108a43d431bSSoby Mathew .endm 109a43d431bSSoby Mathew 110a43d431bSSoby Mathew .macro print_callee_saved_regs 111a43d431bSSoby Mathew sub sp, sp, CALLEE_SAVED_REG_SIZE 112a43d431bSSoby Mathew stp x19, x20, [sp] 113a43d431bSSoby Mathew stp x21, x22, [sp, #(REG_SIZE * 2)] 114a43d431bSSoby Mathew stp x23, x24, [sp, #(REG_SIZE * 4)] 115a43d431bSSoby Mathew stp x25, x26, [sp, #(REG_SIZE * 6)] 116a43d431bSSoby Mathew stp x27, x28, [sp, #(REG_SIZE * 8)] 117a43d431bSSoby Mathew stp x29, x30, [sp, #(REG_SIZE * 10)] 118a43d431bSSoby Mathew adr x0, callee_saved_regs 119a43d431bSSoby Mathew mov x1, sp 120a43d431bSSoby Mathew bl print_string_value 121a43d431bSSoby Mathew add sp, sp, #CALLEE_SAVED_REG_SIZE 122a43d431bSSoby Mathew .endm 123a43d431bSSoby Mathew 124a43d431bSSoby Mathew .macro print_el3_sys_regs 125a43d431bSSoby Mathew sub sp, sp, #EL3_SYS_REG_SIZE 126a43d431bSSoby Mathew mrs x9, scr_el3 127a43d431bSSoby Mathew mrs x10, sctlr_el3 128a43d431bSSoby Mathew mrs x11, cptr_el3 129a43d431bSSoby Mathew mrs x12, tcr_el3 130a43d431bSSoby Mathew mrs x13, daif 131a43d431bSSoby Mathew mrs x14, mair_el3 132a43d431bSSoby Mathew mrs x15, spsr_el3 /*save the elr and spsr regs seperately*/ 133a43d431bSSoby Mathew mrs x16, elr_el3 134a43d431bSSoby Mathew mrs x17, ttbr0_el3 135a43d431bSSoby Mathew mrs x8, esr_el3 136a43d431bSSoby Mathew mrs x7, far_el3 137a43d431bSSoby Mathew 138a43d431bSSoby Mathew stp x9, x10, [sp] 139a43d431bSSoby Mathew stp x11, x12, [sp, #(REG_SIZE * 2)] 140a43d431bSSoby Mathew stp x13, x14, [sp, #(REG_SIZE * 4)] 141a43d431bSSoby Mathew stp x15, x16, [sp, #(REG_SIZE * 6)] 142a43d431bSSoby Mathew stp x17, x8, [sp, #(REG_SIZE * 8)] 143a43d431bSSoby Mathew stp x0, x7, [sp, #(REG_SIZE * 10)] /* sp_el3 is in x0 */ 144a43d431bSSoby Mathew 145a43d431bSSoby Mathew adr x0, el3_sys_regs 146a43d431bSSoby Mathew mov x1, sp 147a43d431bSSoby Mathew bl print_string_value 148a43d431bSSoby Mathew add sp, sp, #EL3_SYS_REG_SIZE 149a43d431bSSoby Mathew .endm 150a43d431bSSoby Mathew 151a43d431bSSoby Mathew .macro print_non_el3_sys_0_regs 152a43d431bSSoby Mathew sub sp, sp, #NON_EL3_SYS_0_REG_SIZE 153a43d431bSSoby Mathew mrs x9, spsr_el1 154a43d431bSSoby Mathew mrs x10, elr_el1 155a43d431bSSoby Mathew mrs x11, spsr_abt 156a43d431bSSoby Mathew mrs x12, spsr_und 157a43d431bSSoby Mathew mrs x13, spsr_irq 158a43d431bSSoby Mathew mrs x14, spsr_fiq 159a43d431bSSoby Mathew mrs x15, sctlr_el1 160a43d431bSSoby Mathew mrs x16, actlr_el1 161a43d431bSSoby Mathew mrs x17, cpacr_el1 162a43d431bSSoby Mathew mrs x8, csselr_el1 163a43d431bSSoby Mathew 164a43d431bSSoby Mathew stp x9, x10, [sp] 165a43d431bSSoby Mathew stp x11, x12, [sp, #(REG_SIZE * 2)] 166a43d431bSSoby Mathew stp x13, x14, [sp, #(REG_SIZE * 4)] 167a43d431bSSoby Mathew stp x15, x16, [sp, #(REG_SIZE * 6)] 168a43d431bSSoby Mathew stp x17, x8, [sp, #(REG_SIZE * 8)] 169a43d431bSSoby Mathew 170a43d431bSSoby Mathew mrs x10, sp_el1 171a43d431bSSoby Mathew mrs x11, esr_el1 172a43d431bSSoby Mathew mrs x12, ttbr0_el1 173a43d431bSSoby Mathew mrs x13, ttbr1_el1 174a43d431bSSoby Mathew mrs x14, mair_el1 175a43d431bSSoby Mathew mrs x15, amair_el1 176a43d431bSSoby Mathew mrs x16, tcr_el1 177a43d431bSSoby Mathew mrs x17, tpidr_el1 178a43d431bSSoby Mathew 179a43d431bSSoby Mathew stp x10, x11, [sp, #(REG_SIZE * 10)] 180a43d431bSSoby Mathew stp x12, x13, [sp, #(REG_SIZE * 12)] 181a43d431bSSoby Mathew stp x14, x15, [sp, #(REG_SIZE * 14)] 182a43d431bSSoby Mathew stp x16, x17, [sp, #(REG_SIZE * 16)] 183a43d431bSSoby Mathew 184a43d431bSSoby Mathew adr x0, non_el3_sys_0_regs 185a43d431bSSoby Mathew mov x1, sp 186a43d431bSSoby Mathew bl print_string_value 187a43d431bSSoby Mathew add sp, sp, #NON_EL3_SYS_0_REG_SIZE 188a43d431bSSoby Mathew .endm 189a43d431bSSoby Mathew 190a43d431bSSoby Mathew .macro print_non_el3_sys_1_regs 191a43d431bSSoby Mathew sub sp, sp, #NON_EL3_SYS_1_REG_SIZE 192a43d431bSSoby Mathew 193a43d431bSSoby Mathew mrs x9, tpidr_el0 194a43d431bSSoby Mathew mrs x10, tpidrro_el0 195a43d431bSSoby Mathew mrs x11, dacr32_el2 196a43d431bSSoby Mathew mrs x12, ifsr32_el2 197a43d431bSSoby Mathew mrs x13, par_el1 198a43d431bSSoby Mathew mrs x14, far_el1 199a43d431bSSoby Mathew mrs x15, afsr0_el1 200a43d431bSSoby Mathew mrs x16, afsr1_el1 201a43d431bSSoby Mathew mrs x17, contextidr_el1 202a43d431bSSoby Mathew mrs x8, vbar_el1 203a43d431bSSoby Mathew 204a43d431bSSoby Mathew stp x9, x10, [sp] 205a43d431bSSoby Mathew stp x11, x12, [sp, #(REG_SIZE * 2)] 206a43d431bSSoby Mathew stp x13, x14, [sp, #(REG_SIZE * 4)] 207a43d431bSSoby Mathew stp x15, x16, [sp, #(REG_SIZE * 6)] 208a43d431bSSoby Mathew stp x17, x8, [sp, #(REG_SIZE * 8)] 209a43d431bSSoby Mathew 210a43d431bSSoby Mathew mrs x10, cntp_ctl_el0 211a43d431bSSoby Mathew mrs x11, cntp_cval_el0 212a43d431bSSoby Mathew mrs x12, cntv_ctl_el0 213a43d431bSSoby Mathew mrs x13, cntv_cval_el0 214a43d431bSSoby Mathew mrs x14, cntkctl_el1 215a43d431bSSoby Mathew mrs x15, fpexc32_el2 216a43d431bSSoby Mathew mrs x8, sp_el0 217a43d431bSSoby Mathew 218a43d431bSSoby Mathew stp x10, x11, [sp, #(REG_SIZE *10)] 219a43d431bSSoby Mathew stp x12, x13, [sp, #(REG_SIZE * 12)] 220a43d431bSSoby Mathew stp x14, x15, [sp, #(REG_SIZE * 14)] 221a43d431bSSoby Mathew stp x8, xzr, [sp, #(REG_SIZE * 16)] 222a43d431bSSoby Mathew 223a43d431bSSoby Mathew adr x0, non_el3_sys_1_regs 224a43d431bSSoby Mathew mov x1, sp 225a43d431bSSoby Mathew bl print_string_value 226a43d431bSSoby Mathew add sp, sp, #NON_EL3_SYS_1_REG_SIZE 227a43d431bSSoby Mathew .endm 228a43d431bSSoby Mathew 229a43d431bSSoby Mathew .macro init_crash_stack 230a43d431bSSoby Mathew msr cntfrq_el0, x0 /* we can corrupt this reg to free up x0 */ 231a43d431bSSoby Mathew mrs x0, tpidr_el3 232a43d431bSSoby Mathew 233a43d431bSSoby Mathew /* Check if tpidr is initialized */ 234a43d431bSSoby Mathew cbz x0, infinite_loop 235a43d431bSSoby Mathew 236*5e910074SAndrew Thoelke ldr x0, [x0, #CPU_DATA_CRASH_STACK_OFFSET] 237a43d431bSSoby Mathew /* store the x30 and sp to stack */ 238a43d431bSSoby Mathew str x30, [x0, #-(REG_SIZE)]! 239a43d431bSSoby Mathew mov x30, sp 240a43d431bSSoby Mathew str x30, [x0, #-(REG_SIZE)]! 241a43d431bSSoby Mathew mov sp, x0 242a43d431bSSoby Mathew mrs x0, cntfrq_el0 243a43d431bSSoby Mathew .endm 244a43d431bSSoby Mathew 245a43d431bSSoby Mathew /* --------------------------------------------------- 246a43d431bSSoby Mathew * The below function initializes the crash dump stack , 247a43d431bSSoby Mathew * and prints the system state. This function 248a43d431bSSoby Mathew * will not return. 249a43d431bSSoby Mathew * --------------------------------------------------- 250a43d431bSSoby Mathew */ 251a43d431bSSoby Mathewfunc dump_state_and_die 252a43d431bSSoby Mathew init_crash_stack 253a43d431bSSoby Mathew print_caller_saved_regs 254a43d431bSSoby Mathew b print_state 255a43d431bSSoby Mathew 256a43d431bSSoby Mathewfunc dump_intr_state_and_die 257a43d431bSSoby Mathew init_crash_stack 258a43d431bSSoby Mathew print_caller_saved_regs 259a43d431bSSoby Mathew plat_print_gic_regs /* fall through to print_state */ 260a43d431bSSoby Mathew 261a43d431bSSoby Mathewprint_state: 262a43d431bSSoby Mathew /* copy the original x30 from stack */ 263a43d431bSSoby Mathew ldr x30, [sp, #REG_SIZE] 264a43d431bSSoby Mathew print_callee_saved_regs 265a43d431bSSoby Mathew /* copy the original SP_EL3 from stack to x0 and rewind stack */ 266a43d431bSSoby Mathew ldr x0, [sp], #(REG_SIZE * 2) 267a43d431bSSoby Mathew print_el3_sys_regs 268a43d431bSSoby Mathew print_non_el3_sys_0_regs 269a43d431bSSoby Mathew print_non_el3_sys_1_regs 270a43d431bSSoby Mathew 2719c22b323SAndrew Thoelke#else /* CRASH_REPORING */ 2729c22b323SAndrew Thoelke 2739c22b323SAndrew Thoelkefunc dump_state_and_die 2749c22b323SAndrew Thoelkedump_intr_state_and_die: 2759c22b323SAndrew Thoelke 2769c22b323SAndrew Thoelke#endif /* CRASH_REPORING */ 2779c22b323SAndrew Thoelke 2789c22b323SAndrew Thoelkeinfinite_loop: 279a43d431bSSoby Mathew b infinite_loop 280a43d431bSSoby Mathew 281a43d431bSSoby Mathew 282a43d431bSSoby Mathew#define PCPU_CRASH_STACK_SIZE 0x140 283a43d431bSSoby Mathew 284a43d431bSSoby Mathew /* ----------------------------------------------------- 285a43d431bSSoby Mathew * Per-cpu crash stacks in normal memory. 286a43d431bSSoby Mathew * ----------------------------------------------------- 287a43d431bSSoby Mathew */ 288a43d431bSSoby Mathewdeclare_stack pcpu_crash_stack, tzfw_normal_stacks, \ 289a43d431bSSoby Mathew PCPU_CRASH_STACK_SIZE, PLATFORM_CORE_COUNT 290*5e910074SAndrew Thoelke 291*5e910074SAndrew Thoelke /* ----------------------------------------------------- 292*5e910074SAndrew Thoelke * Provides each CPU with a small stacks for reporting 293*5e910074SAndrew Thoelke * unhandled exceptions, and stores the stack address 294*5e910074SAndrew Thoelke * in cpu_data 295*5e910074SAndrew Thoelke * 296*5e910074SAndrew Thoelke * This can be called without a runtime stack 297*5e910074SAndrew Thoelke * clobbers: x0 - x4 298*5e910074SAndrew Thoelke * ----------------------------------------------------- 299*5e910074SAndrew Thoelke */ 300*5e910074SAndrew Thoelkefunc init_crash_reporting 301*5e910074SAndrew Thoelke mov x4, x30 302*5e910074SAndrew Thoelke mov x2, #0 303*5e910074SAndrew Thoelke adr x3, pcpu_crash_stack 304*5e910074SAndrew Thoelkeinit_crash_loop: 305*5e910074SAndrew Thoelke mov x0, x2 306*5e910074SAndrew Thoelke bl _cpu_data_by_index 307*5e910074SAndrew Thoelke add x3, x3, #PCPU_CRASH_STACK_SIZE 308*5e910074SAndrew Thoelke str x3, [x0, #CPU_DATA_CRASH_STACK_OFFSET] 309*5e910074SAndrew Thoelke add x2, x2, #1 310*5e910074SAndrew Thoelke cmp x2, #PLATFORM_CORE_COUNT 311*5e910074SAndrew Thoelke b.lo init_crash_loop 312*5e910074SAndrew Thoelke ret x4 313