1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <common/bl_common.h> 11#include <el3_common_macros.S> 12#include <lib/pmf/pmf_asm_macros.S> 13#include <lib/runtime_instr.h> 14#include <lib/xlat_tables/xlat_mmu_helpers.h> 15 16 .globl bl31_entrypoint 17 .globl bl31_warm_entrypoint 18 19 /* ----------------------------------------------------- 20 * bl31_entrypoint() is the cold boot entrypoint, 21 * executed only by the primary cpu. 22 * ----------------------------------------------------- 23 */ 24 25func bl31_entrypoint 26 /* --------------------------------------------------------------- 27 * Stash the previous bootloader arguments x0 - x3 for later use. 28 * --------------------------------------------------------------- 29 */ 30 mov x20, x0 31 mov x21, x1 32 mov x22, x2 33 mov x23, x3 34 35 /* -------------------------------------------------------------------- 36 * If PIE is enabled, fixup the Global descriptor Table and dynamic 37 * relocations 38 * -------------------------------------------------------------------- 39 */ 40#if ENABLE_PIE 41 mov_imm x0, BL31_BASE 42 mov_imm x1, BL31_LIMIT 43 bl fixup_gdt_reloc 44#endif /* ENABLE_PIE */ 45 46#if !RESET_TO_BL31 47 /* --------------------------------------------------------------------- 48 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 49 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 50 * and primary/secondary CPU logic should not be executed in this case. 51 * 52 * Also, assume that the previous bootloader has already initialised the 53 * SCTLR_EL3, including the endianness, and has initialised the memory. 54 * --------------------------------------------------------------------- 55 */ 56 el3_entrypoint_common \ 57 _init_sctlr=0 \ 58 _warm_boot_mailbox=0 \ 59 _secondary_cold_boot=0 \ 60 _init_memory=0 \ 61 _init_c_runtime=1 \ 62 _exception_vectors=runtime_exceptions 63#else 64 65 /* --------------------------------------------------------------------- 66 * For RESET_TO_BL31 systems which have a programmable reset address, 67 * bl31_entrypoint() is executed only on the cold boot path so we can 68 * skip the warm boot mailbox mechanism. 69 * --------------------------------------------------------------------- 70 */ 71 el3_entrypoint_common \ 72 _init_sctlr=1 \ 73 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 74 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 75 _init_memory=1 \ 76 _init_c_runtime=1 \ 77 _exception_vectors=runtime_exceptions 78 79 /* --------------------------------------------------------------------- 80 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 81 * there's no argument to relay from a previous bootloader. Zero the 82 * arguments passed to the platform layer to reflect that. 83 * --------------------------------------------------------------------- 84 */ 85 mov x20, 0 86 mov x21, 0 87 mov x22, 0 88 mov x23, 0 89#endif /* RESET_TO_BL31 */ 90 91 /* -------------------------------------------------------------------- 92 * Perform BL31 setup 93 * -------------------------------------------------------------------- 94 */ 95 mov x0, x20 96 mov x1, x21 97 mov x2, x22 98 mov x3, x23 99 bl bl31_setup 100 101 /* -------------------------------------------------------------------- 102 * Enable pointer authentication 103 * -------------------------------------------------------------------- 104 */ 105#if ENABLE_PAUTH 106 mrs x0, sctlr_el3 107 orr x0, x0, #SCTLR_EnIA_BIT 108 msr sctlr_el3, x0 109 isb 110#endif /* ENABLE_PAUTH */ 111 112 /* -------------------------------------------------------------------- 113 * Jump to main function. 114 * -------------------------------------------------------------------- 115 */ 116 bl bl31_main 117 118 /* -------------------------------------------------------------------- 119 * Clean the .data & .bss sections to main memory. This ensures 120 * that any global data which was initialised by the primary CPU 121 * is visible to secondary CPUs before they enable their data 122 * caches and participate in coherency. 123 * -------------------------------------------------------------------- 124 */ 125 adr x0, __DATA_START__ 126 adr x1, __DATA_END__ 127 sub x1, x1, x0 128 bl clean_dcache_range 129 130 adr x0, __BSS_START__ 131 adr x1, __BSS_END__ 132 sub x1, x1, x0 133 bl clean_dcache_range 134 135 b el3_exit 136endfunc bl31_entrypoint 137 138 /* -------------------------------------------------------------------- 139 * This CPU has been physically powered up. It is either resuming from 140 * suspend or has simply been turned on. In both cases, call the BL31 141 * warmboot entrypoint 142 * -------------------------------------------------------------------- 143 */ 144func bl31_warm_entrypoint 145#if ENABLE_RUNTIME_INSTRUMENTATION 146 147 /* 148 * This timestamp update happens with cache off. The next 149 * timestamp collection will need to do cache maintenance prior 150 * to timestamp update. 151 */ 152 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR 153 mrs x1, cntpct_el0 154 str x1, [x0] 155#endif 156 157 /* 158 * On the warm boot path, most of the EL3 initialisations performed by 159 * 'el3_entrypoint_common' must be skipped: 160 * 161 * - Only when the platform bypasses the BL1/BL31 entrypoint by 162 * programming the reset address do we need to initialise SCTLR_EL3. 163 * In other cases, we assume this has been taken care by the 164 * entrypoint code. 165 * 166 * - No need to determine the type of boot, we know it is a warm boot. 167 * 168 * - Do not try to distinguish between primary and secondary CPUs, this 169 * notion only exists for a cold boot. 170 * 171 * - No need to initialise the memory or the C runtime environment, 172 * it has been done once and for all on the cold boot path. 173 */ 174 el3_entrypoint_common \ 175 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 176 _warm_boot_mailbox=0 \ 177 _secondary_cold_boot=0 \ 178 _init_memory=0 \ 179 _init_c_runtime=0 \ 180 _exception_vectors=runtime_exceptions 181 182 /* 183 * We're about to enable MMU and participate in PSCI state coordination. 184 * 185 * The PSCI implementation invokes platform routines that enable CPUs to 186 * participate in coherency. On a system where CPUs are not 187 * cache-coherent without appropriate platform specific programming, 188 * having caches enabled until such time might lead to coherency issues 189 * (resulting from stale data getting speculatively fetched, among 190 * others). Therefore we keep data caches disabled even after enabling 191 * the MMU for such platforms. 192 * 193 * On systems with hardware-assisted coherency, or on single cluster 194 * platforms, such platform specific programming is not required to 195 * enter coherency (as CPUs already are); and there's no reason to have 196 * caches disabled either. 197 */ 198#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY 199 mov x0, xzr 200#else 201 mov x0, #DISABLE_DCACHE 202#endif 203 bl bl31_plat_enable_mmu 204 205 /* -------------------------------------------------------------------- 206 * Enable pointer authentication 207 * -------------------------------------------------------------------- 208 */ 209#if ENABLE_PAUTH 210 bl pauth_load_bl_apiakey 211 212 mrs x0, sctlr_el3 213 orr x0, x0, #SCTLR_EnIA_BIT 214 msr sctlr_el3, x0 215 isb 216#endif /* ENABLE_PAUTH */ 217 218 bl psci_warmboot_entrypoint 219 220#if ENABLE_RUNTIME_INSTRUMENTATION 221 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI 222 mov x19, x0 223 224 /* 225 * Invalidate before updating timestamp to ensure previous timestamp 226 * updates on the same cache line with caches disabled are properly 227 * seen by the same core. Without the cache invalidate, the core might 228 * write into a stale cache line. 229 */ 230 mov x1, #PMF_TS_SIZE 231 mov x20, x30 232 bl inv_dcache_range 233 mov x30, x20 234 235 mrs x0, cntpct_el0 236 str x0, [x19] 237#endif 238 b el3_exit 239endfunc bl31_warm_entrypoint 240