1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34 35 .globl bl31_entrypoint 36 37 38 /* ----------------------------------------------------- 39 * bl31_entrypoint() is the cold boot entrypoint, 40 * executed only by the primary cpu. 41 * ----------------------------------------------------- 42 */ 43 44func bl31_entrypoint 45 /* --------------------------------------------------------------- 46 * Preceding bootloader has populated x0 with a pointer to a 47 * 'bl31_params' structure & x1 with a pointer to platform 48 * specific structure 49 * --------------------------------------------------------------- 50 */ 51#if !RESET_TO_BL31 52 mov x20, x0 53 mov x21, x1 54#else 55 56 /* ----------------------------------------------------- 57 * Perform any processor specific actions upon reset 58 * e.g. cache, tlb invalidations etc. Override the 59 * Boot ROM(BL0) programming sequence 60 * ----------------------------------------------------- 61 */ 62 bl cpu_reset_handler 63#endif 64 65 /* --------------------------------------------- 66 * Enable the instruction cache. 67 * --------------------------------------------- 68 */ 69 mrs x1, sctlr_el3 70 orr x1, x1, #SCTLR_I_BIT 71 msr sctlr_el3, x1 72 isb 73 74 /* --------------------------------------------- 75 * Set the exception vector and zero tpidr_el3 76 * until the crash reporting is set up 77 * --------------------------------------------- 78 */ 79 adr x1, runtime_exceptions 80 msr vbar_el3, x1 81 msr tpidr_el3, xzr 82 83 /* --------------------------------------------------------------------- 84 * The initial state of the Architectural feature trap register 85 * (CPTR_EL3) is unknown and it must be set to a known state. All 86 * feature traps are disabled. Some bits in this register are marked as 87 * Reserved and should not be modified. 88 * 89 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 90 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 91 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 92 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 93 * access to trace functionality is not supported, this bit is RES0. 94 * CPTR_EL3.TFP: This causes instructions that access the registers 95 * associated with Floating Point and Advanced SIMD execution to trap 96 * to EL3 when executed from any exception level, unless trapped to EL1 97 * or EL2. 98 * --------------------------------------------------------------------- 99 */ 100 mrs x1, cptr_el3 101 bic w1, w1, #TCPAC_BIT 102 bic w1, w1, #TTA_BIT 103 bic w1, w1, #TFP_BIT 104 msr cptr_el3, x1 105 106#if RESET_TO_BL31 107 wait_for_entrypoint 108 bl platform_mem_init 109#else 110 /* --------------------------------------------- 111 * This is BL31 which is expected to be executed 112 * only by the primary cpu (at least for now). 113 * So, make sure no secondary has lost its way. 114 * --------------------------------------------- 115 */ 116 mrs x0, mpidr_el1 117 bl platform_is_primary_cpu 118 cbz x0, _panic 119#endif 120 121 /* --------------------------------------------- 122 * Zero out NOBITS sections. There are 2 of them: 123 * - the .bss section; 124 * - the coherent memory section. 125 * --------------------------------------------- 126 */ 127 ldr x0, =__BSS_START__ 128 ldr x1, =__BSS_SIZE__ 129 bl zeromem16 130 131 ldr x0, =__COHERENT_RAM_START__ 132 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 133 bl zeromem16 134 135 /* --------------------------------------------- 136 * Initialise cpu_data and crash reporting 137 * --------------------------------------------- 138 */ 139#if CRASH_REPORTING 140 bl init_crash_reporting 141#endif 142 bl init_cpu_data_ptr 143 144 /* --------------------------------------------- 145 * Use SP_EL0 for the C runtime stack. 146 * --------------------------------------------- 147 */ 148 msr spsel, #0 149 150 /* -------------------------------------------- 151 * Give ourselves a small coherent stack to 152 * ease the pain of initializing the MMU 153 * -------------------------------------------- 154 */ 155 mrs x0, mpidr_el1 156 bl platform_set_coherent_stack 157 158 /* --------------------------------------------- 159 * Perform platform specific early arch. setup 160 * --------------------------------------------- 161 */ 162#if RESET_TO_BL31 163 mov x0, 0 164 mov x1, 0 165#else 166 mov x0, x20 167 mov x1, x21 168#endif 169 170 bl bl31_early_platform_setup 171 bl bl31_plat_arch_setup 172 173 /* --------------------------------------------- 174 * Give ourselves a stack allocated in Normal 175 * -IS-WBWA memory 176 * --------------------------------------------- 177 */ 178 mrs x0, mpidr_el1 179 bl platform_set_stack 180 181 /* --------------------------------------------- 182 * Jump to main function. 183 * --------------------------------------------- 184 */ 185 bl bl31_main 186 187 b el3_exit 188 189_panic: 190 wfi 191 b _panic 192