1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <bl_common.h> 33#include <el3_common_macros.S> 34#include <xlat_tables.h> 35 36 .globl bl31_entrypoint 37 .globl bl31_warm_entrypoint 38 39 /* ----------------------------------------------------- 40 * bl31_entrypoint() is the cold boot entrypoint, 41 * executed only by the primary cpu. 42 * ----------------------------------------------------- 43 */ 44 45func bl31_entrypoint 46#if !RESET_TO_BL31 47 /* --------------------------------------------------------------- 48 * Preceding bootloader has populated x0 with a pointer to a 49 * 'bl31_params' structure & x1 with a pointer to platform 50 * specific structure 51 * --------------------------------------------------------------- 52 */ 53 mov x20, x0 54 mov x21, x1 55 56 /* --------------------------------------------------------------------- 57 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 58 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 59 * and primary/secondary CPU logic should not be executed in this case. 60 * 61 * Also, assume that the previous bootloader has already set up the CPU 62 * endianness and has initialised the memory. 63 * --------------------------------------------------------------------- 64 */ 65 el3_entrypoint_common \ 66 _set_endian=0 \ 67 _warm_boot_mailbox=0 \ 68 _secondary_cold_boot=0 \ 69 _init_memory=0 \ 70 _init_c_runtime=1 \ 71 _exception_vectors=runtime_exceptions 72 73 /* --------------------------------------------------------------------- 74 * Relay the previous bootloader's arguments to the platform layer 75 * --------------------------------------------------------------------- 76 */ 77 mov x0, x20 78 mov x1, x21 79#else 80 /* --------------------------------------------------------------------- 81 * For RESET_TO_BL31 systems which have a programmable reset address, 82 * bl31_entrypoint() is executed only on the cold boot path so we can 83 * skip the warm boot mailbox mechanism. 84 * --------------------------------------------------------------------- 85 */ 86 el3_entrypoint_common \ 87 _set_endian=1 \ 88 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 89 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 90 _init_memory=1 \ 91 _init_c_runtime=1 \ 92 _exception_vectors=runtime_exceptions 93 94 /* --------------------------------------------------------------------- 95 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 96 * there's no argument to relay from a previous bootloader. Zero the 97 * arguments passed to the platform layer to reflect that. 98 * --------------------------------------------------------------------- 99 */ 100 mov x0, 0 101 mov x1, 0 102#endif /* RESET_TO_BL31 */ 103 104 /* --------------------------------------------- 105 * Perform platform specific early arch. setup 106 * --------------------------------------------- 107 */ 108 bl bl31_early_platform_setup 109 bl bl31_plat_arch_setup 110 111 /* --------------------------------------------- 112 * Jump to main function. 113 * --------------------------------------------- 114 */ 115 bl bl31_main 116 117 /* ------------------------------------------------------------- 118 * Clean the .data & .bss sections to main memory. This ensures 119 * that any global data which was initialised by the primary CPU 120 * is visible to secondary CPUs before they enable their data 121 * caches and participate in coherency. 122 * ------------------------------------------------------------- 123 */ 124 adr x0, __DATA_START__ 125 adr x1, __DATA_END__ 126 sub x1, x1, x0 127 bl clean_dcache_range 128 129 adr x0, __BSS_START__ 130 adr x1, __BSS_END__ 131 sub x1, x1, x0 132 bl clean_dcache_range 133 134 b el3_exit 135endfunc bl31_entrypoint 136 137 /* -------------------------------------------------------------------- 138 * This CPU has been physically powered up. It is either resuming from 139 * suspend or has simply been turned on. In both cases, call the BL31 140 * warmboot entrypoint 141 * -------------------------------------------------------------------- 142 */ 143func bl31_warm_entrypoint 144 /* 145 * On the warm boot path, most of the EL3 initialisations performed by 146 * 'el3_entrypoint_common' must be skipped: 147 * 148 * - Only when the platform bypasses the BL1/BL31 entrypoint by 149 * programming the reset address do we need to set the CPU endianness. 150 * In other cases, we assume this has been taken care by the 151 * entrypoint code. 152 * 153 * - No need to determine the type of boot, we know it is a warm boot. 154 * 155 * - Do not try to distinguish between primary and secondary CPUs, this 156 * notion only exists for a cold boot. 157 * 158 * - No need to initialise the memory or the C runtime environment, 159 * it has been done once and for all on the cold boot path. 160 */ 161 el3_entrypoint_common \ 162 _set_endian=PROGRAMMABLE_RESET_ADDRESS \ 163 _warm_boot_mailbox=0 \ 164 _secondary_cold_boot=0 \ 165 _init_memory=0 \ 166 _init_c_runtime=0 \ 167 _exception_vectors=runtime_exceptions 168 169 /* -------------------------------------------- 170 * Enable the MMU with the DCache disabled. It 171 * is safe to use stacks allocated in normal 172 * memory as a result. All memory accesses are 173 * marked nGnRnE when the MMU is disabled. So 174 * all the stack writes will make it to memory. 175 * All memory accesses are marked Non-cacheable 176 * when the MMU is enabled but D$ is disabled. 177 * So used stack memory is guaranteed to be 178 * visible immediately after the MMU is enabled 179 * Enabling the DCache at the same time as the 180 * MMU can lead to speculatively fetched and 181 * possibly stale stack memory being read from 182 * other caches. This can lead to coherency 183 * issues. 184 * -------------------------------------------- 185 */ 186 mov x0, #DISABLE_DCACHE 187 bl bl31_plat_enable_mmu 188 189 bl psci_warmboot_entrypoint 190 191 b el3_exit 192endfunc bl31_warm_entrypoint 193