1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <bl_common.h> 32#include <platform.h> 33#include <arch.h> 34#include "cm_macros.S" 35 36 37 .globl bl31_entrypoint 38 39 40 .section .text, "ax"; .align 3 41 42 /* ----------------------------------------------------- 43 * bl31_entrypoint() is the cold boot entrypoint, 44 * executed only by the primary cpu. 45 * ----------------------------------------------------- 46 */ 47 48bl31_entrypoint: ; .type bl31_entrypoint, %function 49 /* --------------------------------------------- 50 * BL2 has populated x0,x3,x4 with the opcode 51 * indicating BL31 should be run, memory layout 52 * of the trusted SRAM available to BL31 and 53 * information about running the non-trusted 54 * software already loaded by BL2. 55 * --------------------------------------------- 56 */ 57 58 /* --------------------------------------------- 59 * Set the exception vector to something sane. 60 * --------------------------------------------- 61 */ 62 adr x1, early_exceptions 63 msr vbar_el3, x1 64 65 /* --------------------------------------------------------------------- 66 * The initial state of the Architectural feature trap register 67 * (CPTR_EL3) is unknown and it must be set to a known state. All 68 * feature traps are disabled. Some bits in this register are marked as 69 * Reserved and should not be modified. 70 * 71 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 72 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 73 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 74 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 75 * access to trace functionality is not supported, this bit is RES0. 76 * CPTR_EL3.TFP: This causes instructions that access the registers 77 * associated with Floating Point and Advanced SIMD execution to trap 78 * to EL3 when executed from any exception level, unless trapped to EL1 79 * or EL2. 80 * --------------------------------------------------------------------- 81 */ 82 mrs x1, cptr_el3 83 bic w1, w1, #TCPAC_BIT 84 bic w1, w1, #TTA_BIT 85 bic w1, w1, #TFP_BIT 86 msr cptr_el3, x1 87 88 /* --------------------------------------------- 89 * Enable the instruction cache. 90 * --------------------------------------------- 91 */ 92 mrs x1, sctlr_el3 93 orr x1, x1, #SCTLR_I_BIT 94 msr sctlr_el3, x1 95 96 isb 97 98 /* --------------------------------------------- 99 * Check the opcodes out of paranoia. 100 * --------------------------------------------- 101 */ 102 mov x19, #RUN_IMAGE 103 cmp x0, x19 104 b.ne _panic 105 mov x20, x3 106 mov x21, x4 107 108 /* --------------------------------------------- 109 * This is BL31 which is expected to be executed 110 * only by the primary cpu (at least for now). 111 * So, make sure no secondary has lost its way. 112 * --------------------------------------------- 113 */ 114 bl read_mpidr 115 mov x19, x0 116 bl platform_is_primary_cpu 117 cbz x0, _panic 118 119 /* --------------------------------------------- 120 * Zero out NOBITS sections. There are 2 of them: 121 * - the .bss section; 122 * - the coherent memory section. 123 * --------------------------------------------- 124 */ 125 ldr x0, =__BSS_START__ 126 ldr x1, =__BSS_SIZE__ 127 bl zeromem16 128 129 ldr x0, =__COHERENT_RAM_START__ 130 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 131 bl zeromem16 132 133 /* --------------------------------------------- 134 * Use SP_EL0 for the C runtime stack. 135 * --------------------------------------------- 136 */ 137 msr spsel, #0 138 139 /* -------------------------------------------- 140 * Give ourselves a small coherent stack to 141 * ease the pain of initializing the MMU 142 * -------------------------------------------- 143 */ 144 mov x0, x19 145 bl platform_set_coherent_stack 146 147 /* --------------------------------------------- 148 * Perform platform specific early arch. setup 149 * --------------------------------------------- 150 */ 151 mov x0, x20 152 mov x1, x21 153 bl bl31_early_platform_setup 154 bl bl31_plat_arch_setup 155 156 /* --------------------------------------------- 157 * Give ourselves a stack allocated in Normal 158 * -IS-WBWA memory 159 * --------------------------------------------- 160 */ 161 mov x0, x19 162 bl platform_set_stack 163 164 /* --------------------------------------------- 165 * Jump to main function. 166 * --------------------------------------------- 167 */ 168 bl bl31_main 169 170 /* --------------------------------------------- 171 * Use the more complex exception vectors now 172 * that context management is setup. SP_EL3 is 173 * pointing to a 'cpu_context' structure which 174 * has an exception stack allocated. Since 175 * we're just about to leave this EL with ERET, 176 * we don't need an ISB here 177 * --------------------------------------------- 178 */ 179 adr x1, runtime_exceptions 180 msr vbar_el3, x1 181 182 zero_callee_saved_regs 183 b el3_exit 184 185_panic: 186 wfi 187 b _panic 188