1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <cm_macros.S> 35 36 37 .globl bl31_entrypoint 38 39 40 /* ----------------------------------------------------- 41 * bl31_entrypoint() is the cold boot entrypoint, 42 * executed only by the primary cpu. 43 * ----------------------------------------------------- 44 */ 45 46func bl31_entrypoint 47 /* --------------------------------------------- 48 * BL2 has populated x0 with the opcode 49 * indicating BL31 should be run, x3 with 50 * a pointer to a 'bl31_args' structure & x4 51 * with any other optional information 52 * --------------------------------------------- 53 */ 54 55 /* --------------------------------------------- 56 * Set the exception vector to something sane. 57 * --------------------------------------------- 58 */ 59 adr x1, early_exceptions 60 msr vbar_el3, x1 61 62 /* --------------------------------------------------------------------- 63 * The initial state of the Architectural feature trap register 64 * (CPTR_EL3) is unknown and it must be set to a known state. All 65 * feature traps are disabled. Some bits in this register are marked as 66 * Reserved and should not be modified. 67 * 68 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 69 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 70 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 71 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 72 * access to trace functionality is not supported, this bit is RES0. 73 * CPTR_EL3.TFP: This causes instructions that access the registers 74 * associated with Floating Point and Advanced SIMD execution to trap 75 * to EL3 when executed from any exception level, unless trapped to EL1 76 * or EL2. 77 * --------------------------------------------------------------------- 78 */ 79 mrs x1, cptr_el3 80 bic w1, w1, #TCPAC_BIT 81 bic w1, w1, #TTA_BIT 82 bic w1, w1, #TFP_BIT 83 msr cptr_el3, x1 84 85 /* --------------------------------------------- 86 * Enable the instruction cache. 87 * --------------------------------------------- 88 */ 89 mrs x1, sctlr_el3 90 orr x1, x1, #SCTLR_I_BIT 91 msr sctlr_el3, x1 92 isb 93 94 /* --------------------------------------------- 95 * Check the opcodes out of paranoia. 96 * --------------------------------------------- 97 */ 98 mov x19, #RUN_IMAGE 99 cmp x0, x19 100 b.ne _panic 101 mov x20, x3 102 mov x21, x4 103 104 /* --------------------------------------------- 105 * This is BL31 which is expected to be executed 106 * only by the primary cpu (at least for now). 107 * So, make sure no secondary has lost its way. 108 * --------------------------------------------- 109 */ 110 bl read_mpidr 111 mov x19, x0 112 bl platform_is_primary_cpu 113 cbz x0, _panic 114 115 /* --------------------------------------------- 116 * Zero out NOBITS sections. There are 2 of them: 117 * - the .bss section; 118 * - the coherent memory section. 119 * --------------------------------------------- 120 */ 121 ldr x0, =__BSS_START__ 122 ldr x1, =__BSS_SIZE__ 123 bl zeromem16 124 125 ldr x0, =__COHERENT_RAM_START__ 126 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 127 bl zeromem16 128 129 /* --------------------------------------------- 130 * Use SP_EL0 for the C runtime stack. 131 * --------------------------------------------- 132 */ 133 msr spsel, #0 134 135 /* -------------------------------------------- 136 * Give ourselves a small coherent stack to 137 * ease the pain of initializing the MMU 138 * -------------------------------------------- 139 */ 140 mov x0, x19 141 bl platform_set_coherent_stack 142 143 /* --------------------------------------------- 144 * Perform platform specific early arch. setup 145 * --------------------------------------------- 146 */ 147 mov x0, x20 148 mov x1, x21 149 bl bl31_early_platform_setup 150 bl bl31_plat_arch_setup 151 152 /* --------------------------------------------- 153 * Give ourselves a stack allocated in Normal 154 * -IS-WBWA memory 155 * --------------------------------------------- 156 */ 157 mov x0, x19 158 bl platform_set_stack 159 160 /* --------------------------------------------- 161 * Jump to main function. 162 * --------------------------------------------- 163 */ 164 bl bl31_main 165 166 zero_callee_saved_regs 167 b el3_exit 168 169_panic: 170 wfi 171 b _panic 172