1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34 35 .globl bl31_entrypoint 36 37 38 /* ----------------------------------------------------- 39 * bl31_entrypoint() is the cold boot entrypoint, 40 * executed only by the primary cpu. 41 * ----------------------------------------------------- 42 */ 43 44func bl31_entrypoint 45 /* --------------------------------------------------------------- 46 * Preceding bootloader has populated x0 with a pointer to a 47 * 'bl31_params' structure & x1 with a pointer to platform 48 * specific structure 49 * --------------------------------------------------------------- 50 */ 51#if !RESET_TO_BL31 52 mov x20, x0 53 mov x21, x1 54#else 55 56 /* ----------------------------------------------------- 57 * Perform any processor specific actions upon reset 58 * e.g. cache, tlb invalidations etc. Override the 59 * Boot ROM(BL0) programming sequence 60 * ----------------------------------------------------- 61 */ 62 bl cpu_reset_handler 63#endif 64 65 /* --------------------------------------------- 66 * Enable the instruction cache. 67 * --------------------------------------------- 68 */ 69 mrs x1, sctlr_el3 70 orr x1, x1, #SCTLR_I_BIT 71 msr sctlr_el3, x1 72 isb 73 74 /* --------------------------------------------- 75 * Initialise cpu_data early to enable crash 76 * reporting to have access to crash stack. 77 * Since crash reporting depends on cpu_data to 78 * report the unhandled exception, not 79 * doing so can lead to recursive exceptions due 80 * to a NULL TPIDR_EL3 81 * --------------------------------------------- 82 */ 83 bl init_cpu_data_ptr 84 85 /* --------------------------------------------- 86 * Set the exception vector. 87 * --------------------------------------------- 88 */ 89 adr x1, runtime_exceptions 90 msr vbar_el3, x1 91 92 /* --------------------------------------------------------------------- 93 * The initial state of the Architectural feature trap register 94 * (CPTR_EL3) is unknown and it must be set to a known state. All 95 * feature traps are disabled. Some bits in this register are marked as 96 * Reserved and should not be modified. 97 * 98 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 99 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 100 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 101 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 102 * access to trace functionality is not supported, this bit is RES0. 103 * CPTR_EL3.TFP: This causes instructions that access the registers 104 * associated with Floating Point and Advanced SIMD execution to trap 105 * to EL3 when executed from any exception level, unless trapped to EL1 106 * or EL2. 107 * --------------------------------------------------------------------- 108 */ 109 mrs x1, cptr_el3 110 bic w1, w1, #TCPAC_BIT 111 bic w1, w1, #TTA_BIT 112 bic w1, w1, #TFP_BIT 113 msr cptr_el3, x1 114 115#if RESET_TO_BL31 116 /* ------------------------------------------------------- 117 * Will not return from this macro if it is a warm boot. 118 * ------------------------------------------------------- 119 */ 120 wait_for_entrypoint 121 bl platform_mem_init 122#else 123 /* --------------------------------------------- 124 * This is BL31 which is expected to be executed 125 * only by the primary cpu (at least for now). 126 * So, make sure no secondary has lost its way. 127 * --------------------------------------------- 128 */ 129 mrs x0, mpidr_el1 130 bl platform_is_primary_cpu 131 cbz x0, _panic 132#endif 133 134 /* --------------------------------------------- 135 * Zero out NOBITS sections. There are 2 of them: 136 * - the .bss section; 137 * - the coherent memory section. 138 * --------------------------------------------- 139 */ 140 ldr x0, =__BSS_START__ 141 ldr x1, =__BSS_SIZE__ 142 bl zeromem16 143 144 ldr x0, =__COHERENT_RAM_START__ 145 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 146 bl zeromem16 147 148 /* --------------------------------------------- 149 * Use SP_EL0 for the C runtime stack. 150 * --------------------------------------------- 151 */ 152 msr spsel, #0 153 154 /* -------------------------------------------- 155 * Give ourselves a small coherent stack to 156 * ease the pain of initializing the MMU 157 * -------------------------------------------- 158 */ 159 mrs x0, mpidr_el1 160 bl platform_set_coherent_stack 161 162 /* --------------------------------------------- 163 * Perform platform specific early arch. setup 164 * --------------------------------------------- 165 */ 166#if RESET_TO_BL31 167 mov x0, 0 168 mov x1, 0 169#else 170 mov x0, x20 171 mov x1, x21 172#endif 173 174 bl bl31_early_platform_setup 175 bl bl31_plat_arch_setup 176 177 /* --------------------------------------------- 178 * Give ourselves a stack allocated in Normal 179 * -IS-WBWA memory 180 * --------------------------------------------- 181 */ 182 mrs x0, mpidr_el1 183 bl platform_set_stack 184 185 /* --------------------------------------------- 186 * Jump to main function. 187 * --------------------------------------------- 188 */ 189 bl bl31_main 190 191 b el3_exit 192 193_panic: 194 wfi 195 b _panic 196