1/* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <common/bl_common.h> 11#include <el3_common_macros.S> 12#include <lib/pmf/aarch64/pmf_asm_macros.S> 13#include <lib/runtime_instr.h> 14#include <lib/xlat_tables/xlat_mmu_helpers.h> 15 16 .globl bl31_entrypoint 17 .globl bl31_warm_entrypoint 18 19 /* ----------------------------------------------------- 20 * bl31_entrypoint() is the cold boot entrypoint, 21 * executed only by the primary cpu. 22 * ----------------------------------------------------- 23 */ 24 25func bl31_entrypoint 26 /* --------------------------------------------------------------- 27 * Stash the previous bootloader arguments x0 - x3 for later use. 28 * --------------------------------------------------------------- 29 */ 30 mov x20, x0 31 mov x21, x1 32 mov x22, x2 33 mov x23, x3 34 35#if !RESET_TO_BL31 36 /* --------------------------------------------------------------------- 37 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 38 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 39 * and primary/secondary CPU logic should not be executed in this case. 40 * 41 * Also, assume that the previous bootloader has already initialised the 42 * SCTLR_EL3, including the endianness, and has initialised the memory. 43 * --------------------------------------------------------------------- 44 */ 45 el3_entrypoint_common \ 46 _init_sctlr=0 \ 47 _warm_boot_mailbox=0 \ 48 _secondary_cold_boot=0 \ 49 _init_memory=0 \ 50 _init_c_runtime=1 \ 51 _exception_vectors=runtime_exceptions \ 52 _pie_fixup_size=BL31_LIMIT - BL31_BASE 53#else 54 55 /* --------------------------------------------------------------------- 56 * For RESET_TO_BL31 systems which have a programmable reset address, 57 * bl31_entrypoint() is executed only on the cold boot path so we can 58 * skip the warm boot mailbox mechanism. 59 * --------------------------------------------------------------------- 60 */ 61 el3_entrypoint_common \ 62 _init_sctlr=1 \ 63 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 64 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 65 _init_memory=1 \ 66 _init_c_runtime=1 \ 67 _exception_vectors=runtime_exceptions \ 68 _pie_fixup_size=BL31_LIMIT - BL31_BASE 69#endif /* RESET_TO_BL31 */ 70 71 /* -------------------------------------------------------------------- 72 * Perform BL31 setup 73 * -------------------------------------------------------------------- 74 */ 75 mov x0, x20 76 mov x1, x21 77 mov x2, x22 78 mov x3, x23 79 80 /* -------------------------------------------------------------------- 81 * Jump to main function 82 * -------------------------------------------------------------------- 83 */ 84 bl bl31_main 85 86 /* -------------------------------------------------------------------- 87 * Clean the .data & .bss sections to main memory. This ensures 88 * that any global data which was initialised by the primary CPU 89 * is visible to secondary CPUs before they enable their data 90 * caches and participate in coherency. 91 * -------------------------------------------------------------------- 92 */ 93 adrp x0, __DATA_START__ 94 add x0, x0, :lo12:__DATA_START__ 95 adrp x1, __DATA_END__ 96 add x1, x1, :lo12:__DATA_END__ 97 sub x1, x1, x0 98 bl clean_dcache_range 99 100 adrp x0, __BSS_START__ 101 add x0, x0, :lo12:__BSS_START__ 102 adrp x1, __BSS_END__ 103 add x1, x1, :lo12:__BSS_END__ 104 sub x1, x1, x0 105 bl clean_dcache_range 106 107 b el3_exit 108endfunc bl31_entrypoint 109 110 /* -------------------------------------------------------------------- 111 * This CPU has been physically powered up. It is either resuming from 112 * suspend or has simply been turned on. In both cases, call the BL31 113 * warmboot entrypoint 114 * -------------------------------------------------------------------- 115 */ 116func bl31_warm_entrypoint 117#if ENABLE_RUNTIME_INSTRUMENTATION 118 119 /* 120 * This timestamp update happens with cache off. The next 121 * timestamp collection will need to do cache maintenance prior 122 * to timestamp update. 123 */ 124 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR 125 mrs x1, cntpct_el0 126 str x1, [x0] 127#endif 128 129 /* 130 * On the warm boot path, most of the EL3 initialisations performed by 131 * 'el3_entrypoint_common' must be skipped: 132 * 133 * - Only when the platform bypasses the BL1/BL31 entrypoint by 134 * programming the reset address do we need to initialise SCTLR_EL3. 135 * In other cases, we assume this has been taken care by the 136 * entrypoint code. 137 * 138 * - No need to determine the type of boot, we know it is a warm boot. 139 * 140 * - Do not try to distinguish between primary and secondary CPUs, this 141 * notion only exists for a cold boot. 142 * 143 * - No need to initialise the memory or the C runtime environment, 144 * it has been done once and for all on the cold boot path. 145 */ 146 el3_entrypoint_common \ 147 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 148 _warm_boot_mailbox=0 \ 149 _secondary_cold_boot=0 \ 150 _init_memory=0 \ 151 _init_c_runtime=0 \ 152 _exception_vectors=runtime_exceptions \ 153 _pie_fixup_size=0 154 155 bl bl31_warmboot 156 157#if ENABLE_RUNTIME_INSTRUMENTATION 158 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI 159 mov x19, x0 160 161 /* 162 * Invalidate before updating timestamp to ensure previous timestamp 163 * updates on the same cache line with caches disabled are properly 164 * seen by the same core. Without the cache invalidate, the core might 165 * write into a stale cache line. 166 */ 167 mov x1, #PMF_TS_SIZE 168 mov x20, x30 169 bl inv_dcache_range 170 mov x30, x20 171 172 mrs x0, cntpct_el0 173 str x0, [x19] 174#endif 175 b el3_exit 176endfunc bl31_warm_entrypoint 177