1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <bl_common.h> 32#include <platform.h> 33#include <arch.h> 34#include "cm_macros.S" 35 36 37 .globl bl31_entrypoint 38 39 40 .section .text, "ax"; .align 3 41 42 /* ----------------------------------------------------- 43 * bl31_entrypoint() is the cold boot entrypoint, 44 * executed only by the primary cpu. 45 * ----------------------------------------------------- 46 */ 47 48bl31_entrypoint: ; .type bl31_entrypoint, %function 49 /* --------------------------------------------- 50 * BL2 has populated x0 with the opcode 51 * indicating BL31 should be run, x3 with 52 * a pointer to a 'bl31_args' structure & x4 53 * with any other optional information 54 * --------------------------------------------- 55 */ 56 57 /* --------------------------------------------- 58 * Set the exception vector to something sane. 59 * --------------------------------------------- 60 */ 61 adr x1, early_exceptions 62 msr vbar_el3, x1 63 64 /* --------------------------------------------------------------------- 65 * The initial state of the Architectural feature trap register 66 * (CPTR_EL3) is unknown and it must be set to a known state. All 67 * feature traps are disabled. Some bits in this register are marked as 68 * Reserved and should not be modified. 69 * 70 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 71 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 72 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 73 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 74 * access to trace functionality is not supported, this bit is RES0. 75 * CPTR_EL3.TFP: This causes instructions that access the registers 76 * associated with Floating Point and Advanced SIMD execution to trap 77 * to EL3 when executed from any exception level, unless trapped to EL1 78 * or EL2. 79 * --------------------------------------------------------------------- 80 */ 81 mrs x1, cptr_el3 82 bic w1, w1, #TCPAC_BIT 83 bic w1, w1, #TTA_BIT 84 bic w1, w1, #TFP_BIT 85 msr cptr_el3, x1 86 87 /* --------------------------------------------- 88 * Enable the instruction cache. 89 * --------------------------------------------- 90 */ 91 mrs x1, sctlr_el3 92 orr x1, x1, #SCTLR_I_BIT 93 msr sctlr_el3, x1 94 95 isb 96 97 /* --------------------------------------------- 98 * Check the opcodes out of paranoia. 99 * --------------------------------------------- 100 */ 101 mov x19, #RUN_IMAGE 102 cmp x0, x19 103 b.ne _panic 104 mov x20, x3 105 mov x21, x4 106 107 /* --------------------------------------------- 108 * This is BL31 which is expected to be executed 109 * only by the primary cpu (at least for now). 110 * So, make sure no secondary has lost its way. 111 * --------------------------------------------- 112 */ 113 bl read_mpidr 114 mov x19, x0 115 bl platform_is_primary_cpu 116 cbz x0, _panic 117 118 /* --------------------------------------------- 119 * Zero out NOBITS sections. There are 2 of them: 120 * - the .bss section; 121 * - the coherent memory section. 122 * --------------------------------------------- 123 */ 124 ldr x0, =__BSS_START__ 125 ldr x1, =__BSS_SIZE__ 126 bl zeromem16 127 128 ldr x0, =__COHERENT_RAM_START__ 129 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 130 bl zeromem16 131 132 /* --------------------------------------------- 133 * Use SP_EL0 for the C runtime stack. 134 * --------------------------------------------- 135 */ 136 msr spsel, #0 137 138 /* -------------------------------------------- 139 * Give ourselves a small coherent stack to 140 * ease the pain of initializing the MMU 141 * -------------------------------------------- 142 */ 143 mov x0, x19 144 bl platform_set_coherent_stack 145 146 /* --------------------------------------------- 147 * Perform platform specific early arch. setup 148 * --------------------------------------------- 149 */ 150 mov x0, x20 151 mov x1, x21 152 bl bl31_early_platform_setup 153 bl bl31_plat_arch_setup 154 155 /* --------------------------------------------- 156 * Give ourselves a stack allocated in Normal 157 * -IS-WBWA memory 158 * --------------------------------------------- 159 */ 160 mov x0, x19 161 bl platform_set_stack 162 163 /* --------------------------------------------- 164 * Jump to main function. 165 * --------------------------------------------- 166 */ 167 bl bl31_main 168 169 zero_callee_saved_regs 170 b el3_exit 171 172_panic: 173 wfi 174 b _panic 175