1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <bl_common.h> 33#include <el3_common_macros.S> 34 35 .globl bl31_entrypoint 36 37 38 /* ----------------------------------------------------- 39 * bl31_entrypoint() is the cold boot entrypoint, 40 * executed only by the primary cpu. 41 * ----------------------------------------------------- 42 */ 43 44func bl31_entrypoint 45#if !RESET_TO_BL31 46 /* --------------------------------------------------------------- 47 * Preceding bootloader has populated x0 with a pointer to a 48 * 'bl31_params' structure & x1 with a pointer to platform 49 * specific structure 50 * --------------------------------------------------------------- 51 */ 52 mov x20, x0 53 mov x21, x1 54 55 /* --------------------------------------------------------------------- 56 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 57 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 58 * and primary/secondary CPU logic should not be executed in this case. 59 * 60 * Also, assume that the previous bootloader has already set up the CPU 61 * endianness and has initialised the memory. 62 * --------------------------------------------------------------------- 63 */ 64 el3_entrypoint_common \ 65 _set_endian=0 \ 66 _warm_boot_mailbox=0 \ 67 _secondary_cold_boot=0 \ 68 _init_memory=0 \ 69 _init_c_runtime=1 \ 70 _exception_vectors=runtime_exceptions 71 72 /* --------------------------------------------------------------------- 73 * Relay the previous bootloader's arguments to the platform layer 74 * --------------------------------------------------------------------- 75 */ 76 mov x0, x20 77 mov x1, x21 78#else 79 /* --------------------------------------------------------------------- 80 * For RESET_TO_BL31 systems which have a programmable reset address, 81 * bl31_entrypoint() is executed only on the cold boot path so we can 82 * skip the warm boot mailbox mechanism. 83 * --------------------------------------------------------------------- 84 */ 85 el3_entrypoint_common \ 86 _set_endian=1 \ 87 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 88 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 89 _init_memory=1 \ 90 _init_c_runtime=1 \ 91 _exception_vectors=runtime_exceptions 92 93 /* --------------------------------------------------------------------- 94 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 95 * there's no argument to relay from a previous bootloader. Zero the 96 * arguments passed to the platform layer to reflect that. 97 * --------------------------------------------------------------------- 98 */ 99 mov x0, 0 100 mov x1, 0 101#endif /* RESET_TO_BL31 */ 102 103 /* --------------------------------------------- 104 * Perform platform specific early arch. setup 105 * --------------------------------------------- 106 */ 107 bl bl31_early_platform_setup 108 bl bl31_plat_arch_setup 109 110 /* --------------------------------------------- 111 * Jump to main function. 112 * --------------------------------------------- 113 */ 114 bl bl31_main 115 116 /* ------------------------------------------------------------- 117 * Clean the .data & .bss sections to main memory. This ensures 118 * that any global data which was initialised by the primary CPU 119 * is visible to secondary CPUs before they enable their data 120 * caches and participate in coherency. 121 * ------------------------------------------------------------- 122 */ 123 adr x0, __DATA_START__ 124 adr x1, __DATA_END__ 125 sub x1, x1, x0 126 bl clean_dcache_range 127 128 adr x0, __BSS_START__ 129 adr x1, __BSS_END__ 130 sub x1, x1, x0 131 bl clean_dcache_range 132 133 b el3_exit 134endfunc bl31_entrypoint 135