1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <common/bl_common.h> 11#include <el3_common_macros.S> 12#include <lib/pmf/pmf_asm_macros.S> 13#include <lib/runtime_instr.h> 14#include <lib/xlat_tables/xlat_mmu_helpers.h> 15 16 .globl bl31_entrypoint 17 .globl bl31_warm_entrypoint 18 19 /* ----------------------------------------------------- 20 * bl31_entrypoint() is the cold boot entrypoint, 21 * executed only by the primary cpu. 22 * ----------------------------------------------------- 23 */ 24 25func bl31_entrypoint 26 /* --------------------------------------------------------------- 27 * Stash the previous bootloader arguments x0 - x3 for later use. 28 * --------------------------------------------------------------- 29 */ 30 mov x20, x0 31 mov x21, x1 32 mov x22, x2 33 mov x23, x3 34 35 /* -------------------------------------------------------------------- 36 * If PIE is enabled, fixup the Global descriptor Table and dynamic 37 * relocations 38 * -------------------------------------------------------------------- 39 */ 40#if ENABLE_PIE 41 mov_imm x0, BL31_BASE 42 mov_imm x1, BL31_LIMIT 43 bl fixup_gdt_reloc 44#endif /* ENABLE_PIE */ 45 46#if !RESET_TO_BL31 47 /* --------------------------------------------------------------------- 48 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 49 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 50 * and primary/secondary CPU logic should not be executed in this case. 51 * 52 * Also, assume that the previous bootloader has already initialised the 53 * SCTLR_EL3, including the endianness, and has initialised the memory. 54 * --------------------------------------------------------------------- 55 */ 56 el3_entrypoint_common \ 57 _init_sctlr=0 \ 58 _warm_boot_mailbox=0 \ 59 _secondary_cold_boot=0 \ 60 _init_memory=0 \ 61 _init_c_runtime=1 \ 62 _exception_vectors=runtime_exceptions 63#else 64 65 /* --------------------------------------------------------------------- 66 * For RESET_TO_BL31 systems which have a programmable reset address, 67 * bl31_entrypoint() is executed only on the cold boot path so we can 68 * skip the warm boot mailbox mechanism. 69 * --------------------------------------------------------------------- 70 */ 71 el3_entrypoint_common \ 72 _init_sctlr=1 \ 73 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 74 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 75 _init_memory=1 \ 76 _init_c_runtime=1 \ 77 _exception_vectors=runtime_exceptions 78 79 /* --------------------------------------------------------------------- 80 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 81 * there's no argument to relay from a previous bootloader. Zero the 82 * arguments passed to the platform layer to reflect that. 83 * --------------------------------------------------------------------- 84 */ 85 mov x20, 0 86 mov x21, 0 87 mov x22, 0 88 mov x23, 0 89#endif /* RESET_TO_BL31 */ 90 91 /* -------------------------------------------------------------------- 92 * Perform BL31 setup 93 * -------------------------------------------------------------------- 94 */ 95 mov x0, x20 96 mov x1, x21 97 mov x2, x22 98 mov x3, x23 99 bl bl31_setup 100 101#if ENABLE_PAUTH 102 /* -------------------------------------------------------------------- 103 * Program APIAKey_EL1 and enable pointer authentication 104 * -------------------------------------------------------------------- 105 */ 106 bl pauth_init_enable_el3 107#endif /* ENABLE_PAUTH */ 108 109 /* -------------------------------------------------------------------- 110 * Jump to main function 111 * -------------------------------------------------------------------- 112 */ 113 bl bl31_main 114 115 /* -------------------------------------------------------------------- 116 * Clean the .data & .bss sections to main memory. This ensures 117 * that any global data which was initialised by the primary CPU 118 * is visible to secondary CPUs before they enable their data 119 * caches and participate in coherency. 120 * -------------------------------------------------------------------- 121 */ 122 adr x0, __DATA_START__ 123 adr x1, __DATA_END__ 124 sub x1, x1, x0 125 bl clean_dcache_range 126 127 adr x0, __BSS_START__ 128 adr x1, __BSS_END__ 129 sub x1, x1, x0 130 bl clean_dcache_range 131 132 b el3_exit 133endfunc bl31_entrypoint 134 135 /* -------------------------------------------------------------------- 136 * This CPU has been physically powered up. It is either resuming from 137 * suspend or has simply been turned on. In both cases, call the BL31 138 * warmboot entrypoint 139 * -------------------------------------------------------------------- 140 */ 141func bl31_warm_entrypoint 142#if ENABLE_RUNTIME_INSTRUMENTATION 143 144 /* 145 * This timestamp update happens with cache off. The next 146 * timestamp collection will need to do cache maintenance prior 147 * to timestamp update. 148 */ 149 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR 150 mrs x1, cntpct_el0 151 str x1, [x0] 152#endif 153 154 /* 155 * On the warm boot path, most of the EL3 initialisations performed by 156 * 'el3_entrypoint_common' must be skipped: 157 * 158 * - Only when the platform bypasses the BL1/BL31 entrypoint by 159 * programming the reset address do we need to initialise SCTLR_EL3. 160 * In other cases, we assume this has been taken care by the 161 * entrypoint code. 162 * 163 * - No need to determine the type of boot, we know it is a warm boot. 164 * 165 * - Do not try to distinguish between primary and secondary CPUs, this 166 * notion only exists for a cold boot. 167 * 168 * - No need to initialise the memory or the C runtime environment, 169 * it has been done once and for all on the cold boot path. 170 */ 171 el3_entrypoint_common \ 172 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 173 _warm_boot_mailbox=0 \ 174 _secondary_cold_boot=0 \ 175 _init_memory=0 \ 176 _init_c_runtime=0 \ 177 _exception_vectors=runtime_exceptions 178 179 /* 180 * We're about to enable MMU and participate in PSCI state coordination. 181 * 182 * The PSCI implementation invokes platform routines that enable CPUs to 183 * participate in coherency. On a system where CPUs are not 184 * cache-coherent without appropriate platform specific programming, 185 * having caches enabled until such time might lead to coherency issues 186 * (resulting from stale data getting speculatively fetched, among 187 * others). Therefore we keep data caches disabled even after enabling 188 * the MMU for such platforms. 189 * 190 * On systems with hardware-assisted coherency, or on single cluster 191 * platforms, such platform specific programming is not required to 192 * enter coherency (as CPUs already are); and there's no reason to have 193 * caches disabled either. 194 */ 195#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY 196 mov x0, xzr 197#else 198 mov x0, #DISABLE_DCACHE 199#endif 200 bl bl31_plat_enable_mmu 201 202#if ENABLE_PAUTH 203 /* -------------------------------------------------------------------- 204 * Program APIAKey_EL1 and enable pointer authentication 205 * -------------------------------------------------------------------- 206 */ 207 bl pauth_init_enable_el3 208#endif /* ENABLE_PAUTH */ 209 210 bl psci_warmboot_entrypoint 211 212#if ENABLE_RUNTIME_INSTRUMENTATION 213 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI 214 mov x19, x0 215 216 /* 217 * Invalidate before updating timestamp to ensure previous timestamp 218 * updates on the same cache line with caches disabled are properly 219 * seen by the same core. Without the cache invalidate, the core might 220 * write into a stale cache line. 221 */ 222 mov x1, #PMF_TS_SIZE 223 mov x20, x30 224 bl inv_dcache_range 225 mov x30, x20 226 227 mrs x0, cntpct_el0 228 str x0, [x19] 229#endif 230 b el3_exit 231endfunc bl31_warm_entrypoint 232