1*4f6ad66aSAchin Gupta/* 2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved. 3*4f6ad66aSAchin Gupta * 4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 6*4f6ad66aSAchin Gupta * 7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 9*4f6ad66aSAchin Gupta * 10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 13*4f6ad66aSAchin Gupta * 14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 16*4f6ad66aSAchin Gupta * prior written permission. 17*4f6ad66aSAchin Gupta * 18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*4f6ad66aSAchin Gupta */ 30*4f6ad66aSAchin Gupta 31*4f6ad66aSAchin Gupta#include <bl1.h> 32*4f6ad66aSAchin Gupta#include <bl_common.h> 33*4f6ad66aSAchin Gupta#include <platform.h> 34*4f6ad66aSAchin Gupta 35*4f6ad66aSAchin Gupta 36*4f6ad66aSAchin Gupta .globl bl31_entrypoint 37*4f6ad66aSAchin Gupta 38*4f6ad66aSAchin Gupta 39*4f6ad66aSAchin Gupta .section entry_code, "ax"; .align 3 40*4f6ad66aSAchin Gupta 41*4f6ad66aSAchin Gupta /* ----------------------------------------------------- 42*4f6ad66aSAchin Gupta * bl31_entrypoint() is the cold boot entrypoint, 43*4f6ad66aSAchin Gupta * executed only by the primary cpu. 44*4f6ad66aSAchin Gupta * ----------------------------------------------------- 45*4f6ad66aSAchin Gupta */ 46*4f6ad66aSAchin Gupta 47*4f6ad66aSAchin Guptabl31_entrypoint:; .type bl31_entrypoint, %function 48*4f6ad66aSAchin Gupta /* --------------------------------------------- 49*4f6ad66aSAchin Gupta * BL2 has populated x0,x3,x4 with the opcode 50*4f6ad66aSAchin Gupta * indicating BL31 should be run, memory layout 51*4f6ad66aSAchin Gupta * of the trusted SRAM available to BL31 and 52*4f6ad66aSAchin Gupta * information about running the non-trusted 53*4f6ad66aSAchin Gupta * software already loaded by BL2. Check the 54*4f6ad66aSAchin Gupta * opcode out of paranoia. 55*4f6ad66aSAchin Gupta * --------------------------------------------- 56*4f6ad66aSAchin Gupta */ 57*4f6ad66aSAchin Gupta mov x19, #RUN_IMAGE 58*4f6ad66aSAchin Gupta cmp x0, x19 59*4f6ad66aSAchin Gupta b.ne _panic 60*4f6ad66aSAchin Gupta mov x20, x3 61*4f6ad66aSAchin Gupta mov x21, x4 62*4f6ad66aSAchin Gupta 63*4f6ad66aSAchin Gupta /* --------------------------------------------- 64*4f6ad66aSAchin Gupta * This is BL31 which is expected to be executed 65*4f6ad66aSAchin Gupta * only by the primary cpu (at least for now). 66*4f6ad66aSAchin Gupta * So, make sure no secondary has lost its way. 67*4f6ad66aSAchin Gupta * --------------------------------------------- 68*4f6ad66aSAchin Gupta */ 69*4f6ad66aSAchin Gupta bl read_mpidr 70*4f6ad66aSAchin Gupta mov x19, x0 71*4f6ad66aSAchin Gupta bl platform_is_primary_cpu 72*4f6ad66aSAchin Gupta cbz x0, _panic 73*4f6ad66aSAchin Gupta 74*4f6ad66aSAchin Gupta /* -------------------------------------------- 75*4f6ad66aSAchin Gupta * Give ourselves a small coherent stack to 76*4f6ad66aSAchin Gupta * ease the pain of initializing the MMU 77*4f6ad66aSAchin Gupta * -------------------------------------------- 78*4f6ad66aSAchin Gupta */ 79*4f6ad66aSAchin Gupta mov x0, x19 80*4f6ad66aSAchin Gupta bl platform_set_coherent_stack 81*4f6ad66aSAchin Gupta 82*4f6ad66aSAchin Gupta /* --------------------------------------------- 83*4f6ad66aSAchin Gupta * Perform platform specific early arch. setup 84*4f6ad66aSAchin Gupta * --------------------------------------------- 85*4f6ad66aSAchin Gupta */ 86*4f6ad66aSAchin Gupta mov x0, x20 87*4f6ad66aSAchin Gupta mov x1, x21 88*4f6ad66aSAchin Gupta mov x2, x19 89*4f6ad66aSAchin Gupta bl bl31_early_platform_setup 90*4f6ad66aSAchin Gupta bl bl31_plat_arch_setup 91*4f6ad66aSAchin Gupta 92*4f6ad66aSAchin Gupta /* --------------------------------------------- 93*4f6ad66aSAchin Gupta * Give ourselves a stack allocated in Normal 94*4f6ad66aSAchin Gupta * -IS-WBWA memory 95*4f6ad66aSAchin Gupta * --------------------------------------------- 96*4f6ad66aSAchin Gupta */ 97*4f6ad66aSAchin Gupta mov x0, x19 98*4f6ad66aSAchin Gupta bl platform_set_stack 99*4f6ad66aSAchin Gupta 100*4f6ad66aSAchin Gupta /* --------------------------------------------- 101*4f6ad66aSAchin Gupta * Use SP_EL0 to initialize BL31. It allows us 102*4f6ad66aSAchin Gupta * to jump to the next image without having to 103*4f6ad66aSAchin Gupta * come back here to ensure all of the stack's 104*4f6ad66aSAchin Gupta * been popped out. run_image() is not nice 105*4f6ad66aSAchin Gupta * enough to reset the stack pointer before 106*4f6ad66aSAchin Gupta * handing control to the next stage. 107*4f6ad66aSAchin Gupta * --------------------------------------------- 108*4f6ad66aSAchin Gupta */ 109*4f6ad66aSAchin Gupta mov x0, sp 110*4f6ad66aSAchin Gupta msr sp_el0, x0 111*4f6ad66aSAchin Gupta msr spsel, #0 112*4f6ad66aSAchin Gupta isb 113*4f6ad66aSAchin Gupta 114*4f6ad66aSAchin Gupta /* --------------------------------------------- 115*4f6ad66aSAchin Gupta * Jump to main function. 116*4f6ad66aSAchin Gupta * --------------------------------------------- 117*4f6ad66aSAchin Gupta */ 118*4f6ad66aSAchin Gupta bl bl31_main 119*4f6ad66aSAchin Gupta 120*4f6ad66aSAchin Gupta_panic: 121*4f6ad66aSAchin Gupta b _panic 122