xref: /rk3399_ARM-atf/bl2u/bl2u.ld.S (revision f43e09a12e4f4f32185d3e2accceb65895d1f16b) 
1/*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <common/bl_common.ld.h>
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20SECTIONS {
21    RAM_REGION_START = ORIGIN(RAM);
22    RAM_REGION_LENGTH = LENGTH(RAM);
23    . = BL2U_BASE;
24
25    ASSERT(. == ALIGN(PAGE_SIZE),
26        "BL2U_BASE address is not aligned on a page boundary.")
27
28#if SEPARATE_CODE_AND_RODATA
29    .text . : {
30        __TEXT_START__ = .;
31
32        *bl2u_entrypoint.o(.text*)
33        *(SORT_BY_ALIGNMENT(.text*))
34        *(.vectors)
35
36        . = ALIGN(PAGE_SIZE);
37
38        __TEXT_END__ = .;
39    } >RAM
40
41    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
42    .ARM.extab . : {
43        *(.ARM.extab* .gnu.linkonce.armextab.*)
44    } >RAM
45
46    .ARM.exidx . : {
47        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
48    } >RAM
49
50    .rodata . : {
51        __RODATA_START__ = .;
52        *(SORT_BY_ALIGNMENT(.rodata*))
53
54        RODATA_COMMON
55
56        . = ALIGN(PAGE_SIZE);
57        __RODATA_END__ = .;
58    } >RAM
59#else /* SEPARATE_CODE_AND_RODATA */
60    .ro . : {
61        __RO_START__ = .;
62
63        *bl2u_entrypoint.o(.text*)
64        *(SORT_BY_ALIGNMENT(.text*))
65        *(SORT_BY_ALIGNMENT(.rodata*))
66
67        RODATA_COMMON
68
69        *(.vectors)
70
71        __RO_END_UNALIGNED__ = .;
72
73        /*
74         * Memory page(s) mapped to this section will be marked as read-only,
75         * executable. No RW data from the next section must creep in. Ensure
76         * that the rest of the current memory page is unused.
77         */
78        . = ALIGN(PAGE_SIZE);
79
80        __RO_END__ = .;
81    } >RAM
82#endif /* SEPARATE_CODE_AND_RODATA */
83
84    __RW_START__ = .;
85
86    DATA_SECTION >RAM
87    STACK_SECTION >RAM
88    BSS_SECTION >RAM
89    XLAT_TABLE_SECTION >RAM
90
91#if USE_COHERENT_MEM
92    /*
93     * The base address of the coherent memory section must be page-aligned to
94     * guarantee that the coherent data are stored on their own pages and are
95     * not mixed with normal data.  This is required to set up the correct
96     * memory attributes for the coherent data page tables.
97     */
98    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
99        __COHERENT_RAM_START__ = .;
100        *(.tzfw_coherent_mem)
101        __COHERENT_RAM_END_UNALIGNED__ = .;
102
103        /*
104         * Memory page(s) mapped to this section will be marked as device
105         * memory. No other unexpected data must creep in. Ensure the rest of
106         * the current memory page is unused.
107         */
108        . = ALIGN(PAGE_SIZE);
109
110        __COHERENT_RAM_END__ = .;
111    } >RAM
112#endif /* USE_COHERENT_MEM */
113
114    __RW_END__ = .;
115    __BL2U_END__ = .;
116
117    __BSS_SIZE__ = SIZEOF(.bss);
118
119    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
120    RAM_REGION_END = .;
121}
122