1/* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <common/bl_common.ld.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 13OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 14ENTRY(bl2u_entrypoint) 15 16MEMORY { 17 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE 18} 19 20 21SECTIONS 22{ 23 . = BL2U_BASE; 24 ASSERT(. == ALIGN(PAGE_SIZE), 25 "BL2U_BASE address is not aligned on a page boundary.") 26 27#if SEPARATE_CODE_AND_RODATA 28 .text . : { 29 __TEXT_START__ = .; 30 *bl2u_entrypoint.o(.text*) 31 *(SORT_BY_ALIGNMENT(.text*)) 32 *(.vectors) 33 . = ALIGN(PAGE_SIZE); 34 __TEXT_END__ = .; 35 } >RAM 36 37 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 38 .ARM.extab . : { 39 *(.ARM.extab* .gnu.linkonce.armextab.*) 40 } >RAM 41 42 .ARM.exidx . : { 43 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 44 } >RAM 45 46 .rodata . : { 47 __RODATA_START__ = .; 48 *(SORT_BY_ALIGNMENT(.rodata*)) 49 . = ALIGN(PAGE_SIZE); 50 __RODATA_END__ = .; 51 } >RAM 52#else 53 ro . : { 54 __RO_START__ = .; 55 *bl2u_entrypoint.o(.text*) 56 *(SORT_BY_ALIGNMENT(.text*)) 57 *(SORT_BY_ALIGNMENT(.rodata*)) 58 59 *(.vectors) 60 __RO_END_UNALIGNED__ = .; 61 /* 62 * Memory page(s) mapped to this section will be marked as 63 * read-only, executable. No RW data from the next section must 64 * creep in. Ensure the rest of the current memory page is unused. 65 */ 66 . = ALIGN(PAGE_SIZE); 67 __RO_END__ = .; 68 } >RAM 69#endif 70 71 /* 72 * Define a linker symbol to mark start of the RW memory area for this 73 * image. 74 */ 75 __RW_START__ = . ; 76 77 /* 78 * .data must be placed at a lower address than the stacks if the stack 79 * protector is enabled. Alternatively, the .data.stack_protector_canary 80 * section can be placed independently of the main .data section. 81 */ 82 .data . : { 83 __DATA_START__ = .; 84 *(SORT_BY_ALIGNMENT(.data*)) 85 __DATA_END__ = .; 86 } >RAM 87 88 stacks (NOLOAD) : { 89 __STACKS_START__ = .; 90 *(tzfw_normal_stacks) 91 __STACKS_END__ = .; 92 } >RAM 93 94 /* 95 * The .bss section gets initialised to 0 at runtime. 96 * Its base address should be 16-byte aligned for better performance of the 97 * zero-initialization code. 98 */ 99 .bss : ALIGN(16) { 100 __BSS_START__ = .; 101 *(SORT_BY_ALIGNMENT(.bss*)) 102 *(COMMON) 103 __BSS_END__ = .; 104 } >RAM 105 106 XLAT_TABLE_SECTION >RAM 107 108#if USE_COHERENT_MEM 109 /* 110 * The base address of the coherent memory section must be page-aligned (4K) 111 * to guarantee that the coherent data are stored on their own pages and 112 * are not mixed with normal data. This is required to set up the correct 113 * memory attributes for the coherent data page tables. 114 */ 115 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 116 __COHERENT_RAM_START__ = .; 117 *(tzfw_coherent_mem) 118 __COHERENT_RAM_END_UNALIGNED__ = .; 119 /* 120 * Memory page(s) mapped to this section will be marked 121 * as device memory. No other unexpected data must creep in. 122 * Ensure the rest of the current memory page is unused. 123 */ 124 . = ALIGN(PAGE_SIZE); 125 __COHERENT_RAM_END__ = .; 126 } >RAM 127#endif 128 129 /* 130 * Define a linker symbol to mark end of the RW memory area for this 131 * image. 132 */ 133 __RW_END__ = .; 134 __BL2U_END__ = .; 135 136 __BSS_SIZE__ = SIZEOF(.bss); 137 138 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") 139} 140