1/* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl2u_entrypoint) 36 37MEMORY { 38 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE 39} 40 41 42SECTIONS 43{ 44 . = BL2U_BASE; 45 ASSERT(. == ALIGN(4096), 46 "BL2U_BASE address is not aligned on a page boundary.") 47 48#if SEPARATE_CODE_AND_RODATA 49 .text . : { 50 __TEXT_START__ = .; 51 *bl2u_entrypoint.o(.text*) 52 *(.text*) 53 *(.vectors) 54 . = NEXT(4096); 55 __TEXT_END__ = .; 56 } >RAM 57 58 .rodata . : { 59 __RODATA_START__ = .; 60 *(.rodata*) 61 . = NEXT(4096); 62 __RODATA_END__ = .; 63 } >RAM 64#else 65 ro . : { 66 __RO_START__ = .; 67 *bl2u_entrypoint.o(.text*) 68 *(.text*) 69 *(.rodata*) 70 71 *(.vectors) 72 __RO_END_UNALIGNED__ = .; 73 /* 74 * Memory page(s) mapped to this section will be marked as 75 * read-only, executable. No RW data from the next section must 76 * creep in. Ensure the rest of the current memory page is unused. 77 */ 78 . = NEXT(4096); 79 __RO_END__ = .; 80 } >RAM 81#endif 82 83 /* 84 * Define a linker symbol to mark start of the RW memory area for this 85 * image. 86 */ 87 __RW_START__ = . ; 88 89 /* 90 * .data must be placed at a lower address than the stacks if the stack 91 * protector is enabled. Alternatively, the .data.stack_protector_canary 92 * section can be placed independently of the main .data section. 93 */ 94 .data . : { 95 __DATA_START__ = .; 96 *(.data*) 97 __DATA_END__ = .; 98 } >RAM 99 100 stacks (NOLOAD) : { 101 __STACKS_START__ = .; 102 *(tzfw_normal_stacks) 103 __STACKS_END__ = .; 104 } >RAM 105 106 /* 107 * The .bss section gets initialised to 0 at runtime. 108 * Its base address should be 16-byte aligned for better performance of the 109 * zero-initialization code. 110 */ 111 .bss : ALIGN(16) { 112 __BSS_START__ = .; 113 *(SORT_BY_ALIGNMENT(.bss*)) 114 *(COMMON) 115 __BSS_END__ = .; 116 } >RAM 117 118 /* 119 * The xlat_table section is for full, aligned page tables (4K). 120 * Removing them from .bss avoids forcing 4K alignment on 121 * the .bss section and eliminates the unecessary zero init 122 */ 123 xlat_table (NOLOAD) : { 124 *(xlat_table) 125 } >RAM 126 127#if USE_COHERENT_MEM 128 /* 129 * The base address of the coherent memory section must be page-aligned (4K) 130 * to guarantee that the coherent data are stored on their own pages and 131 * are not mixed with normal data. This is required to set up the correct 132 * memory attributes for the coherent data page tables. 133 */ 134 coherent_ram (NOLOAD) : ALIGN(4096) { 135 __COHERENT_RAM_START__ = .; 136 *(tzfw_coherent_mem) 137 __COHERENT_RAM_END_UNALIGNED__ = .; 138 /* 139 * Memory page(s) mapped to this section will be marked 140 * as device memory. No other unexpected data must creep in. 141 * Ensure the rest of the current memory page is unused. 142 */ 143 . = NEXT(4096); 144 __COHERENT_RAM_END__ = .; 145 } >RAM 146#endif 147 148 /* 149 * Define a linker symbol to mark end of the RW memory area for this 150 * image. 151 */ 152 __RW_END__ = .; 153 __BL2U_END__ = .; 154 155 __BSS_SIZE__ = SIZEOF(.bss); 156 157 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") 158} 159