xref: /rk3399_ARM-atf/bl2u/bl2u.ld.S (revision 6bb49c876c7593ed5f61c20ef3d989dcff8e8d8c) 
1/*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <common/bl_common.ld.h>
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20SECTIONS {
21    . = BL2U_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL2U_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29
30        *bl2u_entrypoint.o(.text*)
31        *(SORT_BY_ALIGNMENT(.text*))
32        *(.vectors)
33
34        . = ALIGN(PAGE_SIZE);
35
36        __TEXT_END__ = .;
37    } >RAM
38
39    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
40    .ARM.extab . : {
41        *(.ARM.extab* .gnu.linkonce.armextab.*)
42    } >RAM
43
44    .ARM.exidx . : {
45        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
46    } >RAM
47
48    .rodata . : {
49        __RODATA_START__ = .;
50        *(SORT_BY_ALIGNMENT(.rodata*))
51
52        RODATA_COMMON
53
54        . = ALIGN(PAGE_SIZE);
55        __RODATA_END__ = .;
56    } >RAM
57#else /* SEPARATE_CODE_AND_RODATA */
58    .ro . : {
59        __RO_START__ = .;
60
61        *bl2u_entrypoint.o(.text*)
62        *(SORT_BY_ALIGNMENT(.text*))
63        *(SORT_BY_ALIGNMENT(.rodata*))
64
65        RODATA_COMMON
66
67        *(.vectors)
68
69        __RO_END_UNALIGNED__ = .;
70
71        /*
72         * Memory page(s) mapped to this section will be marked as read-only,
73         * executable. No RW data from the next section must creep in. Ensure
74         * that the rest of the current memory page is unused.
75         */
76        . = ALIGN(PAGE_SIZE);
77
78        __RO_END__ = .;
79    } >RAM
80#endif /* SEPARATE_CODE_AND_RODATA */
81
82    __RW_START__ = .;
83
84    DATA_SECTION >RAM
85    STACK_SECTION >RAM
86    BSS_SECTION >RAM
87    XLAT_TABLE_SECTION >RAM
88
89#if USE_COHERENT_MEM
90    /*
91     * The base address of the coherent memory section must be page-aligned to
92     * guarantee that the coherent data are stored on their own pages and are
93     * not mixed with normal data.  This is required to set up the correct
94     * memory attributes for the coherent data page tables.
95     */
96    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
97        __COHERENT_RAM_START__ = .;
98        *(.tzfw_coherent_mem)
99        __COHERENT_RAM_END_UNALIGNED__ = .;
100
101        /*
102         * Memory page(s) mapped to this section will be marked as device
103         * memory. No other unexpected data must creep in. Ensure the rest of
104         * the current memory page is unused.
105         */
106        . = ALIGN(PAGE_SIZE);
107
108        __COHERENT_RAM_END__ = .;
109    } >RAM
110#endif /* USE_COHERENT_MEM */
111
112    __RW_END__ = .;
113    __BL2U_END__ = .;
114
115    __BSS_SIZE__ = SIZEOF(.bss);
116
117    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
118}
119