xref: /rk3399_ARM-atf/bl2u/bl2u.ld.S (revision 3ba55a3c5fa260c9218be1adff8f39fc2a568d68) 
1/*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <common/bl_common.ld.h>
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20
21SECTIONS
22{
23    . = BL2U_BASE;
24    ASSERT(. == ALIGN(PAGE_SIZE),
25           "BL2U_BASE address is not aligned on a page boundary.")
26
27#if SEPARATE_CODE_AND_RODATA
28    .text . : {
29        __TEXT_START__ = .;
30        *bl2u_entrypoint.o(.text*)
31        *(SORT_BY_ALIGNMENT(.text*))
32        *(.vectors)
33        . = ALIGN(PAGE_SIZE);
34        __TEXT_END__ = .;
35     } >RAM
36
37     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
38     .ARM.extab . : {
39        *(.ARM.extab* .gnu.linkonce.armextab.*)
40     } >RAM
41
42     .ARM.exidx . : {
43        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
44     } >RAM
45
46    .rodata . : {
47        __RODATA_START__ = .;
48        *(SORT_BY_ALIGNMENT(.rodata*))
49
50	RODATA_COMMON
51
52        . = ALIGN(PAGE_SIZE);
53        __RODATA_END__ = .;
54    } >RAM
55#else
56    ro . : {
57        __RO_START__ = .;
58        *bl2u_entrypoint.o(.text*)
59        *(SORT_BY_ALIGNMENT(.text*))
60        *(SORT_BY_ALIGNMENT(.rodata*))
61
62	RODATA_COMMON
63
64        *(.vectors)
65        __RO_END_UNALIGNED__ = .;
66        /*
67         * Memory page(s) mapped to this section will be marked as
68         * read-only, executable.  No RW data from the next section must
69         * creep in.  Ensure the rest of the current memory page is unused.
70         */
71        . = ALIGN(PAGE_SIZE);
72        __RO_END__ = .;
73    } >RAM
74#endif
75
76    /*
77     * Define a linker symbol to mark start of the RW memory area for this
78     * image.
79     */
80    __RW_START__ = . ;
81
82    /*
83     * .data must be placed at a lower address than the stacks if the stack
84     * protector is enabled. Alternatively, the .data.stack_protector_canary
85     * section can be placed independently of the main .data section.
86     */
87    .data . : {
88        __DATA_START__ = .;
89        *(SORT_BY_ALIGNMENT(.data*))
90        __DATA_END__ = .;
91    } >RAM
92
93    stacks (NOLOAD) : {
94        __STACKS_START__ = .;
95        *(tzfw_normal_stacks)
96        __STACKS_END__ = .;
97    } >RAM
98
99    BSS_SECTION >RAM
100    XLAT_TABLE_SECTION >RAM
101
102#if USE_COHERENT_MEM
103    /*
104     * The base address of the coherent memory section must be page-aligned (4K)
105     * to guarantee that the coherent data are stored on their own pages and
106     * are not mixed with normal data.  This is required to set up the correct
107     * memory attributes for the coherent data page tables.
108     */
109    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
110        __COHERENT_RAM_START__ = .;
111        *(tzfw_coherent_mem)
112        __COHERENT_RAM_END_UNALIGNED__ = .;
113        /*
114         * Memory page(s) mapped to this section will be marked
115         * as device memory.  No other unexpected data must creep in.
116         * Ensure the rest of the current memory page is unused.
117         */
118        . = ALIGN(PAGE_SIZE);
119        __COHERENT_RAM_END__ = .;
120    } >RAM
121#endif
122
123    /*
124     * Define a linker symbol to mark end of the RW memory area for this
125     * image.
126     */
127    __RW_END__ = .;
128    __BL2U_END__ = .;
129
130    __BSS_SIZE__ = SIZEOF(.bss);
131
132    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
133}
134