1*9003fa0bSYatharth Kochar/* 2*9003fa0bSYatharth Kochar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*9003fa0bSYatharth Kochar * 4*9003fa0bSYatharth Kochar * Redistribution and use in source and binary forms, with or without 5*9003fa0bSYatharth Kochar * modification, are permitted provided that the following conditions are met: 6*9003fa0bSYatharth Kochar * 7*9003fa0bSYatharth Kochar * Redistributions of source code must retain the above copyright notice, this 8*9003fa0bSYatharth Kochar * list of conditions and the following disclaimer. 9*9003fa0bSYatharth Kochar * 10*9003fa0bSYatharth Kochar * Redistributions in binary form must reproduce the above copyright notice, 11*9003fa0bSYatharth Kochar * this list of conditions and the following disclaimer in the documentation 12*9003fa0bSYatharth Kochar * and/or other materials provided with the distribution. 13*9003fa0bSYatharth Kochar * 14*9003fa0bSYatharth Kochar * Neither the name of ARM nor the names of its contributors may be used 15*9003fa0bSYatharth Kochar * to endorse or promote products derived from this software without specific 16*9003fa0bSYatharth Kochar * prior written permission. 17*9003fa0bSYatharth Kochar * 18*9003fa0bSYatharth Kochar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*9003fa0bSYatharth Kochar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*9003fa0bSYatharth Kochar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*9003fa0bSYatharth Kochar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*9003fa0bSYatharth Kochar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*9003fa0bSYatharth Kochar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*9003fa0bSYatharth Kochar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*9003fa0bSYatharth Kochar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*9003fa0bSYatharth Kochar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*9003fa0bSYatharth Kochar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*9003fa0bSYatharth Kochar * POSSIBILITY OF SUCH DAMAGE. 29*9003fa0bSYatharth Kochar */ 30*9003fa0bSYatharth Kochar 31*9003fa0bSYatharth Kochar#include <platform_def.h> 32*9003fa0bSYatharth Kochar 33*9003fa0bSYatharth KocharOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34*9003fa0bSYatharth KocharOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35*9003fa0bSYatharth KocharENTRY(bl2u_entrypoint) 36*9003fa0bSYatharth Kochar 37*9003fa0bSYatharth KocharMEMORY { 38*9003fa0bSYatharth Kochar RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE 39*9003fa0bSYatharth Kochar} 40*9003fa0bSYatharth Kochar 41*9003fa0bSYatharth Kochar 42*9003fa0bSYatharth KocharSECTIONS 43*9003fa0bSYatharth Kochar{ 44*9003fa0bSYatharth Kochar . = BL2U_BASE; 45*9003fa0bSYatharth Kochar ASSERT(. == ALIGN(4096), 46*9003fa0bSYatharth Kochar "BL2U_BASE address is not aligned on a page boundary.") 47*9003fa0bSYatharth Kochar 48*9003fa0bSYatharth Kochar ro . : { 49*9003fa0bSYatharth Kochar __RO_START__ = .; 50*9003fa0bSYatharth Kochar *bl2u_entrypoint.o(.text*) 51*9003fa0bSYatharth Kochar *(.text*) 52*9003fa0bSYatharth Kochar *(.rodata*) 53*9003fa0bSYatharth Kochar 54*9003fa0bSYatharth Kochar *(.vectors) 55*9003fa0bSYatharth Kochar __RO_END_UNALIGNED__ = .; 56*9003fa0bSYatharth Kochar /* 57*9003fa0bSYatharth Kochar * Memory page(s) mapped to this section will be marked as 58*9003fa0bSYatharth Kochar * read-only, executable. No RW data from the next section must 59*9003fa0bSYatharth Kochar * creep in. Ensure the rest of the current memory page is unused. 60*9003fa0bSYatharth Kochar */ 61*9003fa0bSYatharth Kochar . = NEXT(4096); 62*9003fa0bSYatharth Kochar __RO_END__ = .; 63*9003fa0bSYatharth Kochar } >RAM 64*9003fa0bSYatharth Kochar 65*9003fa0bSYatharth Kochar /* 66*9003fa0bSYatharth Kochar * Define a linker symbol to mark start of the RW memory area for this 67*9003fa0bSYatharth Kochar * image. 68*9003fa0bSYatharth Kochar */ 69*9003fa0bSYatharth Kochar __RW_START__ = . ; 70*9003fa0bSYatharth Kochar 71*9003fa0bSYatharth Kochar .data . : { 72*9003fa0bSYatharth Kochar __DATA_START__ = .; 73*9003fa0bSYatharth Kochar *(.data*) 74*9003fa0bSYatharth Kochar __DATA_END__ = .; 75*9003fa0bSYatharth Kochar } >RAM 76*9003fa0bSYatharth Kochar 77*9003fa0bSYatharth Kochar stacks (NOLOAD) : { 78*9003fa0bSYatharth Kochar __STACKS_START__ = .; 79*9003fa0bSYatharth Kochar *(tzfw_normal_stacks) 80*9003fa0bSYatharth Kochar __STACKS_END__ = .; 81*9003fa0bSYatharth Kochar } >RAM 82*9003fa0bSYatharth Kochar 83*9003fa0bSYatharth Kochar /* 84*9003fa0bSYatharth Kochar * The .bss section gets initialised to 0 at runtime. 85*9003fa0bSYatharth Kochar * Its base address must be 16-byte aligned. 86*9003fa0bSYatharth Kochar */ 87*9003fa0bSYatharth Kochar .bss : ALIGN(16) { 88*9003fa0bSYatharth Kochar __BSS_START__ = .; 89*9003fa0bSYatharth Kochar *(SORT_BY_ALIGNMENT(.bss*)) 90*9003fa0bSYatharth Kochar *(COMMON) 91*9003fa0bSYatharth Kochar __BSS_END__ = .; 92*9003fa0bSYatharth Kochar } >RAM 93*9003fa0bSYatharth Kochar 94*9003fa0bSYatharth Kochar /* 95*9003fa0bSYatharth Kochar * The xlat_table section is for full, aligned page tables (4K). 96*9003fa0bSYatharth Kochar * Removing them from .bss avoids forcing 4K alignment on 97*9003fa0bSYatharth Kochar * the .bss section and eliminates the unecessary zero init 98*9003fa0bSYatharth Kochar */ 99*9003fa0bSYatharth Kochar xlat_table (NOLOAD) : { 100*9003fa0bSYatharth Kochar *(xlat_table) 101*9003fa0bSYatharth Kochar } >RAM 102*9003fa0bSYatharth Kochar 103*9003fa0bSYatharth Kochar#if USE_COHERENT_MEM 104*9003fa0bSYatharth Kochar /* 105*9003fa0bSYatharth Kochar * The base address of the coherent memory section must be page-aligned (4K) 106*9003fa0bSYatharth Kochar * to guarantee that the coherent data are stored on their own pages and 107*9003fa0bSYatharth Kochar * are not mixed with normal data. This is required to set up the correct 108*9003fa0bSYatharth Kochar * memory attributes for the coherent data page tables. 109*9003fa0bSYatharth Kochar */ 110*9003fa0bSYatharth Kochar coherent_ram (NOLOAD) : ALIGN(4096) { 111*9003fa0bSYatharth Kochar __COHERENT_RAM_START__ = .; 112*9003fa0bSYatharth Kochar *(tzfw_coherent_mem) 113*9003fa0bSYatharth Kochar __COHERENT_RAM_END_UNALIGNED__ = .; 114*9003fa0bSYatharth Kochar /* 115*9003fa0bSYatharth Kochar * Memory page(s) mapped to this section will be marked 116*9003fa0bSYatharth Kochar * as device memory. No other unexpected data must creep in. 117*9003fa0bSYatharth Kochar * Ensure the rest of the current memory page is unused. 118*9003fa0bSYatharth Kochar */ 119*9003fa0bSYatharth Kochar . = NEXT(4096); 120*9003fa0bSYatharth Kochar __COHERENT_RAM_END__ = .; 121*9003fa0bSYatharth Kochar } >RAM 122*9003fa0bSYatharth Kochar#endif 123*9003fa0bSYatharth Kochar 124*9003fa0bSYatharth Kochar /* 125*9003fa0bSYatharth Kochar * Define a linker symbol to mark end of the RW memory area for this 126*9003fa0bSYatharth Kochar * image. 127*9003fa0bSYatharth Kochar */ 128*9003fa0bSYatharth Kochar __RW_END__ = .; 129*9003fa0bSYatharth Kochar __BL2U_END__ = .; 130*9003fa0bSYatharth Kochar 131*9003fa0bSYatharth Kochar __BSS_SIZE__ = SIZEOF(.bss); 132*9003fa0bSYatharth Kochar 133*9003fa0bSYatharth Kochar ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") 134*9003fa0bSYatharth Kochar} 135