1/* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 .globl bl2u_entrypoint 12 13 14func bl2u_entrypoint 15 /*--------------------------------------------- 16 * Store the extents of the tzram available to 17 * BL2U and other platform specific information 18 * for future use. x0 is currently not used. 19 * --------------------------------------------- 20 */ 21 mov x20, x1 22 mov x21, x2 23 24 /* --------------------------------------------- 25 * Set the exception vector to something sane. 26 * --------------------------------------------- 27 */ 28 adr x0, early_exceptions 29 msr vbar_el1, x0 30 isb 31 32 /* --------------------------------------------- 33 * Enable the SError interrupt now that the 34 * exception vectors have been setup. 35 * --------------------------------------------- 36 */ 37 msr daifclr, #DAIF_ABT_BIT 38 39 /* --------------------------------------------- 40 * Enable the instruction cache, stack pointer 41 * and data access alignment checks 42 * --------------------------------------------- 43 */ 44 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 45 mrs x0, sctlr_el1 46 orr x0, x0, x1 47 msr sctlr_el1, x0 48 isb 49 50 /* --------------------------------------------- 51 * Invalidate the RW memory used by the BL2U 52 * image. This includes the data and NOBITS 53 * sections. This is done to safeguard against 54 * possible corruption of this memory by dirty 55 * cache lines in a system cache as a result of 56 * use by an earlier boot loader stage. 57 * --------------------------------------------- 58 */ 59 adr x0, __RW_START__ 60 adr x1, __RW_END__ 61 sub x1, x1, x0 62 bl inv_dcache_range 63 64 /* --------------------------------------------- 65 * Zero out NOBITS sections. There are 2 of them: 66 * - the .bss section; 67 * - the coherent memory section. 68 * --------------------------------------------- 69 */ 70 ldr x0, =__BSS_START__ 71 ldr x1, =__BSS_SIZE__ 72 bl zeromem 73 74 /* -------------------------------------------- 75 * Allocate a stack whose memory will be marked 76 * as Normal-IS-WBWA when the MMU is enabled. 77 * There is no risk of reading stale stack 78 * memory after enabling the MMU as only the 79 * primary cpu is running at the moment. 80 * -------------------------------------------- 81 */ 82 bl plat_set_my_stack 83 84 /* --------------------------------------------- 85 * Initialize the stack protector canary before 86 * any C code is called. 87 * --------------------------------------------- 88 */ 89#if STACK_PROTECTOR_ENABLED 90 bl update_stack_protector_canary 91#endif 92 93 /* --------------------------------------------- 94 * Perform early platform setup & platform 95 * specific early arch. setup e.g. mmu setup 96 * --------------------------------------------- 97 */ 98 mov x0, x20 99 mov x1, x21 100 bl bl2u_early_platform_setup 101 bl bl2u_plat_arch_setup 102 103 /* --------------------------------------------- 104 * Jump to bl2u_main function. 105 * --------------------------------------------- 106 */ 107 bl bl2u_main 108 109 /* --------------------------------------------- 110 * Should never reach this point. 111 * --------------------------------------------- 112 */ 113 no_ret plat_panic_handler 114 115endfunc bl2u_entrypoint 116