xref: /rk3399_ARM-atf/bl2u/aarch64/bl2u_entrypoint.S (revision 3d8256b2a1ef1195aed86bef7378e83d0a61a91b)
1/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34
35
36	.globl	bl2u_entrypoint
37
38
39func bl2u_entrypoint
40	/*---------------------------------------------
41	 * Store the extents of the tzram available to
42	 * BL2U and other platform specific information
43	 * for future use. x0 is currently not used.
44	 * ---------------------------------------------
45	 */
46	mov	x20, x1
47	mov	x21, x2
48
49	/* ---------------------------------------------
50	 * Set the exception vector to something sane.
51	 * ---------------------------------------------
52	 */
53	adr	x0, early_exceptions
54	msr	vbar_el1, x0
55	isb
56
57	/* ---------------------------------------------
58	 * Enable the SError interrupt now that the
59	 * exception vectors have been setup.
60	 * ---------------------------------------------
61	 */
62	msr	daifclr, #DAIF_ABT_BIT
63
64	/* ---------------------------------------------
65	 * Enable the instruction cache, stack pointer
66	 * and data access alignment checks
67	 * ---------------------------------------------
68	 */
69	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
70	mrs	x0, sctlr_el1
71	orr	x0, x0, x1
72	msr	sctlr_el1, x0
73	isb
74
75	/* ---------------------------------------------
76	 * Invalidate the RW memory used by the BL2U
77	 * image. This includes the data and NOBITS
78	 * sections. This is done to safeguard against
79	 * possible corruption of this memory by dirty
80	 * cache lines in a system cache as a result of
81	 * use by an earlier boot loader stage.
82	 * ---------------------------------------------
83	 */
84	adr	x0, __RW_START__
85	adr	x1, __RW_END__
86	sub	x1, x1, x0
87	bl	inv_dcache_range
88
89	/* ---------------------------------------------
90	 * Zero out NOBITS sections. There are 2 of them:
91	 *   - the .bss section;
92	 *   - the coherent memory section.
93	 * ---------------------------------------------
94	 */
95	ldr	x0, =__BSS_START__
96	ldr	x1, =__BSS_SIZE__
97	bl	zeromem16
98
99	/* --------------------------------------------
100	 * Allocate a stack whose memory will be marked
101	 * as Normal-IS-WBWA when the MMU is enabled.
102	 * There is no risk of reading stale stack
103	 * memory after enabling the MMU as only the
104	 * primary cpu is running at the moment.
105	 * --------------------------------------------
106	 */
107	bl	plat_set_my_stack
108
109	/* ---------------------------------------------
110	 * Perform early platform setup & platform
111	 * specific early arch. setup e.g. mmu setup
112	 * ---------------------------------------------
113	 */
114	mov	x0, x20
115	mov	x1, x21
116	bl	bl2u_early_platform_setup
117	bl	bl2u_plat_arch_setup
118
119	/* ---------------------------------------------
120	 * Jump to bl2u_main function.
121	 * ---------------------------------------------
122	 */
123	bl	bl2u_main
124
125	/* ---------------------------------------------
126	 * Should never reach this point.
127	 * ---------------------------------------------
128	 */
129	no_ret	plat_panic_handler
130
131endfunc bl2u_entrypoint
132