1/* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 .globl bl2u_entrypoint 12 13 14func bl2u_entrypoint 15 /*--------------------------------------------- 16 * Store the extents of the tzram available to 17 * BL2U and other platform specific information 18 * for future use. x0 is currently not used. 19 * --------------------------------------------- 20 */ 21 mov x20, x1 22 mov x21, x2 23 24 /* --------------------------------------------- 25 * Set the exception vector to something sane. 26 * --------------------------------------------- 27 */ 28 adr x0, early_exceptions 29 msr vbar_el1, x0 30 isb 31 32 /* --------------------------------------------- 33 * Enable the SError interrupt now that the 34 * exception vectors have been setup. 35 * --------------------------------------------- 36 */ 37 msr daifclr, #DAIF_ABT_BIT 38 39 /* --------------------------------------------- 40 * Enable the instruction cache, stack pointer 41 * and data access alignment checks and disable 42 * speculative loads. 43 * --------------------------------------------- 44 */ 45 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 46 mrs x0, sctlr_el1 47 orr x0, x0, x1 48#if ENABLE_BTI 49 /* Enable PAC branch type compatibility */ 50 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) 51#endif 52 bic x0, x0, #SCTLR_DSSBS_BIT 53 msr sctlr_el1, x0 54 isb 55 56 /* --------------------------------------------- 57 * Invalidate the RW memory used by the BL2U 58 * image. This includes the data and NOBITS 59 * sections. This is done to safeguard against 60 * possible corruption of this memory by dirty 61 * cache lines in a system cache as a result of 62 * use by an earlier boot loader stage. 63 * --------------------------------------------- 64 */ 65 adr x0, __RW_START__ 66 adr x1, __RW_END__ 67 sub x1, x1, x0 68 bl inv_dcache_range 69 70 /* --------------------------------------------- 71 * Zero out NOBITS sections. There are 2 of them: 72 * - the .bss section; 73 * - the coherent memory section. 74 * --------------------------------------------- 75 */ 76 adrp x0, __BSS_START__ 77 add x0, x0, :lo12:__BSS_START__ 78 adrp x1, __BSS_END__ 79 add x1, x1, :lo12:__BSS_END__ 80 sub x1, x1, x0 81 bl zeromem 82 83 /* -------------------------------------------- 84 * Allocate a stack whose memory will be marked 85 * as Normal-IS-WBWA when the MMU is enabled. 86 * There is no risk of reading stale stack 87 * memory after enabling the MMU as only the 88 * primary cpu is running at the moment. 89 * -------------------------------------------- 90 */ 91 bl plat_set_my_stack 92 93 /* --------------------------------------------- 94 * Initialize the stack protector canary before 95 * any C code is called. 96 * --------------------------------------------- 97 */ 98#if STACK_PROTECTOR_ENABLED 99 bl update_stack_protector_canary 100#endif 101 102 /* --------------------------------------------- 103 * Perform early platform setup & platform 104 * specific early arch. setup e.g. mmu setup 105 * --------------------------------------------- 106 */ 107 mov x0, x20 108 mov x1, x21 109 bl bl2u_early_platform_setup 110 bl bl2u_plat_arch_setup 111 112#if ENABLE_PAUTH 113 /* --------------------------------------------- 114 * Program APIAKey_EL1 115 * and enable pointer authentication. 116 * --------------------------------------------- 117 */ 118 bl pauth_init_enable_el1 119#endif 120 121 /* --------------------------------------------- 122 * Jump to bl2u_main function. 123 * --------------------------------------------- 124 */ 125 bl bl2u_main 126 127 /* --------------------------------------------- 128 * Should never reach this point. 129 * --------------------------------------------- 130 */ 131 no_ret plat_panic_handler 132 133endfunc bl2u_entrypoint 134