1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 .globl bl2u_vector_table 12 .globl bl2u_entrypoint 13 14 15vector_base bl2u_vector_table 16 b bl2u_entrypoint 17 b report_exception /* Undef */ 18 b report_exception /* SVC call */ 19 b report_exception /* Prefetch abort */ 20 b report_exception /* Data abort */ 21 b report_exception /* Reserved */ 22 b report_exception /* IRQ */ 23 b report_exception /* FIQ */ 24 25 26func bl2u_entrypoint 27 /*--------------------------------------------- 28 * Save from r1 the extents of the trusted ram 29 * available to BL2U for future use. 30 * r0 is not currently used. 31 * --------------------------------------------- 32 */ 33 mov r11, r1 34 mov r10, r2 35 36 /* --------------------------------------------- 37 * Set the exception vector to something sane. 38 * --------------------------------------------- 39 */ 40 ldr r0, =bl2u_vector_table 41 stcopr r0, VBAR 42 isb 43 44 /* ----------------------------------------------------- 45 * Enable the instruction cache 46 * ----------------------------------------------------- 47 */ 48 ldcopr r0, SCTLR 49 orr r0, r0, #SCTLR_I_BIT 50 stcopr r0, SCTLR 51 isb 52 53 /* --------------------------------------------- 54 * Since BL2U executes after BL1, it is assumed 55 * here that BL1 has already has done the 56 * necessary register initializations. 57 * --------------------------------------------- 58 */ 59 60 /* --------------------------------------------- 61 * Invalidate the RW memory used by the BL2U 62 * image. This includes the data and NOBITS 63 * sections. This is done to safeguard against 64 * possible corruption of this memory by dirty 65 * cache lines in a system cache as a result of 66 * use by an earlier boot loader stage. 67 * --------------------------------------------- 68 */ 69 ldr r0, =__RW_START__ 70 ldr r1, =__RW_END__ 71 sub r1, r1, r0 72 bl inv_dcache_range 73 74 /* --------------------------------------------- 75 * Zero out NOBITS sections. There are 2 of them: 76 * - the .bss section; 77 * - the coherent memory section. 78 * --------------------------------------------- 79 */ 80 ldr r0, =__BSS_START__ 81 ldr r1, =__BSS_SIZE__ 82 bl zeromem 83 84 /* -------------------------------------------- 85 * Allocate a stack whose memory will be marked 86 * as Normal-IS-WBWA when the MMU is enabled. 87 * There is no risk of reading stale stack 88 * memory after enabling the MMU as only the 89 * primary cpu is running at the moment. 90 * -------------------------------------------- 91 */ 92 bl plat_set_my_stack 93 94 /* --------------------------------------------- 95 * Initialize the stack protector canary before 96 * any C code is called. 97 * --------------------------------------------- 98 */ 99#if STACK_PROTECTOR_ENABLED 100 bl update_stack_protector_canary 101#endif 102 103 /* --------------------------------------------- 104 * Perform early platform setup & platform 105 * specific early arch. setup e.g. mmu setup 106 * --------------------------------------------- 107 */ 108 mov r0, r11 109 mov r1, r10 110 bl bl2u_early_platform_setup 111 bl bl2u_plat_arch_setup 112 113 /* --------------------------------------------- 114 * Jump to main function. 115 * --------------------------------------------- 116 */ 117 bl bl2u_main 118 119 /* --------------------------------------------- 120 * Should never reach this point. 121 * --------------------------------------------- 122 */ 123 no_ret plat_panic_handler 124 125endfunc bl2u_entrypoint 126