1*1bd61d0aSYatharth Kochar/* 2*1bd61d0aSYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*1bd61d0aSYatharth Kochar * 4*1bd61d0aSYatharth Kochar * SPDX-License-Identifier: BSD-3-Clause 5*1bd61d0aSYatharth Kochar */ 6*1bd61d0aSYatharth Kochar 7*1bd61d0aSYatharth Kochar#include <arch.h> 8*1bd61d0aSYatharth Kochar#include <asm_macros.S> 9*1bd61d0aSYatharth Kochar#include <bl_common.h> 10*1bd61d0aSYatharth Kochar 11*1bd61d0aSYatharth Kochar 12*1bd61d0aSYatharth Kochar .globl bl2u_vector_table 13*1bd61d0aSYatharth Kochar .globl bl2u_entrypoint 14*1bd61d0aSYatharth Kochar 15*1bd61d0aSYatharth Kochar 16*1bd61d0aSYatharth Kocharvector_base bl2u_vector_table 17*1bd61d0aSYatharth Kochar b bl2u_entrypoint 18*1bd61d0aSYatharth Kochar b report_exception /* Undef */ 19*1bd61d0aSYatharth Kochar b report_exception /* SVC call */ 20*1bd61d0aSYatharth Kochar b report_exception /* Prefetch abort */ 21*1bd61d0aSYatharth Kochar b report_exception /* Data abort */ 22*1bd61d0aSYatharth Kochar b report_exception /* Reserved */ 23*1bd61d0aSYatharth Kochar b report_exception /* IRQ */ 24*1bd61d0aSYatharth Kochar b report_exception /* FIQ */ 25*1bd61d0aSYatharth Kochar 26*1bd61d0aSYatharth Kochar 27*1bd61d0aSYatharth Kocharfunc bl2u_entrypoint 28*1bd61d0aSYatharth Kochar /*--------------------------------------------- 29*1bd61d0aSYatharth Kochar * Save from r1 the extents of the trusted ram 30*1bd61d0aSYatharth Kochar * available to BL2U for future use. 31*1bd61d0aSYatharth Kochar * r0 is not currently used. 32*1bd61d0aSYatharth Kochar * --------------------------------------------- 33*1bd61d0aSYatharth Kochar */ 34*1bd61d0aSYatharth Kochar mov r11, r1 35*1bd61d0aSYatharth Kochar mov r12, r2 36*1bd61d0aSYatharth Kochar 37*1bd61d0aSYatharth Kochar /* --------------------------------------------- 38*1bd61d0aSYatharth Kochar * Set the exception vector to something sane. 39*1bd61d0aSYatharth Kochar * --------------------------------------------- 40*1bd61d0aSYatharth Kochar */ 41*1bd61d0aSYatharth Kochar ldr r0, =bl2u_vector_table 42*1bd61d0aSYatharth Kochar stcopr r0, VBAR 43*1bd61d0aSYatharth Kochar isb 44*1bd61d0aSYatharth Kochar 45*1bd61d0aSYatharth Kochar /* ----------------------------------------------------- 46*1bd61d0aSYatharth Kochar * Enable the instruction cache 47*1bd61d0aSYatharth Kochar * ----------------------------------------------------- 48*1bd61d0aSYatharth Kochar */ 49*1bd61d0aSYatharth Kochar ldcopr r0, SCTLR 50*1bd61d0aSYatharth Kochar orr r0, r0, #SCTLR_I_BIT 51*1bd61d0aSYatharth Kochar stcopr r0, SCTLR 52*1bd61d0aSYatharth Kochar isb 53*1bd61d0aSYatharth Kochar 54*1bd61d0aSYatharth Kochar /* --------------------------------------------- 55*1bd61d0aSYatharth Kochar * Since BL2U executes after BL1, it is assumed 56*1bd61d0aSYatharth Kochar * here that BL1 has already has done the 57*1bd61d0aSYatharth Kochar * necessary register initializations. 58*1bd61d0aSYatharth Kochar * --------------------------------------------- 59*1bd61d0aSYatharth Kochar */ 60*1bd61d0aSYatharth Kochar 61*1bd61d0aSYatharth Kochar /* --------------------------------------------- 62*1bd61d0aSYatharth Kochar * Invalidate the RW memory used by the BL2U 63*1bd61d0aSYatharth Kochar * image. This includes the data and NOBITS 64*1bd61d0aSYatharth Kochar * sections. This is done to safeguard against 65*1bd61d0aSYatharth Kochar * possible corruption of this memory by dirty 66*1bd61d0aSYatharth Kochar * cache lines in a system cache as a result of 67*1bd61d0aSYatharth Kochar * use by an earlier boot loader stage. 68*1bd61d0aSYatharth Kochar * --------------------------------------------- 69*1bd61d0aSYatharth Kochar */ 70*1bd61d0aSYatharth Kochar ldr r0, =__RW_START__ 71*1bd61d0aSYatharth Kochar ldr r1, =__RW_END__ 72*1bd61d0aSYatharth Kochar sub r1, r1, r0 73*1bd61d0aSYatharth Kochar bl inv_dcache_range 74*1bd61d0aSYatharth Kochar 75*1bd61d0aSYatharth Kochar /* --------------------------------------------- 76*1bd61d0aSYatharth Kochar * Zero out NOBITS sections. There are 2 of them: 77*1bd61d0aSYatharth Kochar * - the .bss section; 78*1bd61d0aSYatharth Kochar * - the coherent memory section. 79*1bd61d0aSYatharth Kochar * --------------------------------------------- 80*1bd61d0aSYatharth Kochar */ 81*1bd61d0aSYatharth Kochar ldr r0, =__BSS_START__ 82*1bd61d0aSYatharth Kochar ldr r1, =__BSS_SIZE__ 83*1bd61d0aSYatharth Kochar bl zeromem 84*1bd61d0aSYatharth Kochar 85*1bd61d0aSYatharth Kochar /* -------------------------------------------- 86*1bd61d0aSYatharth Kochar * Allocate a stack whose memory will be marked 87*1bd61d0aSYatharth Kochar * as Normal-IS-WBWA when the MMU is enabled. 88*1bd61d0aSYatharth Kochar * There is no risk of reading stale stack 89*1bd61d0aSYatharth Kochar * memory after enabling the MMU as only the 90*1bd61d0aSYatharth Kochar * primary cpu is running at the moment. 91*1bd61d0aSYatharth Kochar * -------------------------------------------- 92*1bd61d0aSYatharth Kochar */ 93*1bd61d0aSYatharth Kochar bl plat_set_my_stack 94*1bd61d0aSYatharth Kochar 95*1bd61d0aSYatharth Kochar /* --------------------------------------------- 96*1bd61d0aSYatharth Kochar * Initialize the stack protector canary before 97*1bd61d0aSYatharth Kochar * any C code is called. 98*1bd61d0aSYatharth Kochar * --------------------------------------------- 99*1bd61d0aSYatharth Kochar */ 100*1bd61d0aSYatharth Kochar#if STACK_PROTECTOR_ENABLED 101*1bd61d0aSYatharth Kochar bl update_stack_protector_canary 102*1bd61d0aSYatharth Kochar#endif 103*1bd61d0aSYatharth Kochar 104*1bd61d0aSYatharth Kochar /* --------------------------------------------- 105*1bd61d0aSYatharth Kochar * Perform early platform setup & platform 106*1bd61d0aSYatharth Kochar * specific early arch. setup e.g. mmu setup 107*1bd61d0aSYatharth Kochar * --------------------------------------------- 108*1bd61d0aSYatharth Kochar */ 109*1bd61d0aSYatharth Kochar mov r0, r11 110*1bd61d0aSYatharth Kochar mov r1, r12 111*1bd61d0aSYatharth Kochar bl bl2u_early_platform_setup 112*1bd61d0aSYatharth Kochar bl bl2u_plat_arch_setup 113*1bd61d0aSYatharth Kochar 114*1bd61d0aSYatharth Kochar /* --------------------------------------------- 115*1bd61d0aSYatharth Kochar * Jump to main function. 116*1bd61d0aSYatharth Kochar * --------------------------------------------- 117*1bd61d0aSYatharth Kochar */ 118*1bd61d0aSYatharth Kochar bl bl2u_main 119*1bd61d0aSYatharth Kochar 120*1bd61d0aSYatharth Kochar /* --------------------------------------------- 121*1bd61d0aSYatharth Kochar * Should never reach this point. 122*1bd61d0aSYatharth Kochar * --------------------------------------------- 123*1bd61d0aSYatharth Kochar */ 124*1bd61d0aSYatharth Kochar no_ret plat_panic_handler 125*1bd61d0aSYatharth Kochar 126*1bd61d0aSYatharth Kocharendfunc bl2u_entrypoint 127