11bd61d0aSYatharth Kochar/* 21bd61d0aSYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 31bd61d0aSYatharth Kochar * 41bd61d0aSYatharth Kochar * SPDX-License-Identifier: BSD-3-Clause 51bd61d0aSYatharth Kochar */ 61bd61d0aSYatharth Kochar 71bd61d0aSYatharth Kochar#include <arch.h> 81bd61d0aSYatharth Kochar#include <asm_macros.S> 9*09d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 101bd61d0aSYatharth Kochar 111bd61d0aSYatharth Kochar .globl bl2u_vector_table 121bd61d0aSYatharth Kochar .globl bl2u_entrypoint 131bd61d0aSYatharth Kochar 141bd61d0aSYatharth Kochar 151bd61d0aSYatharth Kocharvector_base bl2u_vector_table 161bd61d0aSYatharth Kochar b bl2u_entrypoint 171bd61d0aSYatharth Kochar b report_exception /* Undef */ 181bd61d0aSYatharth Kochar b report_exception /* SVC call */ 191bd61d0aSYatharth Kochar b report_exception /* Prefetch abort */ 201bd61d0aSYatharth Kochar b report_exception /* Data abort */ 211bd61d0aSYatharth Kochar b report_exception /* Reserved */ 221bd61d0aSYatharth Kochar b report_exception /* IRQ */ 231bd61d0aSYatharth Kochar b report_exception /* FIQ */ 241bd61d0aSYatharth Kochar 251bd61d0aSYatharth Kochar 261bd61d0aSYatharth Kocharfunc bl2u_entrypoint 271bd61d0aSYatharth Kochar /*--------------------------------------------- 281bd61d0aSYatharth Kochar * Save from r1 the extents of the trusted ram 291bd61d0aSYatharth Kochar * available to BL2U for future use. 301bd61d0aSYatharth Kochar * r0 is not currently used. 311bd61d0aSYatharth Kochar * --------------------------------------------- 321bd61d0aSYatharth Kochar */ 331bd61d0aSYatharth Kochar mov r11, r1 345c2c88b5SDouglas Raillard mov r10, r2 351bd61d0aSYatharth Kochar 361bd61d0aSYatharth Kochar /* --------------------------------------------- 371bd61d0aSYatharth Kochar * Set the exception vector to something sane. 381bd61d0aSYatharth Kochar * --------------------------------------------- 391bd61d0aSYatharth Kochar */ 401bd61d0aSYatharth Kochar ldr r0, =bl2u_vector_table 411bd61d0aSYatharth Kochar stcopr r0, VBAR 421bd61d0aSYatharth Kochar isb 431bd61d0aSYatharth Kochar 441bd61d0aSYatharth Kochar /* ----------------------------------------------------- 451bd61d0aSYatharth Kochar * Enable the instruction cache 461bd61d0aSYatharth Kochar * ----------------------------------------------------- 471bd61d0aSYatharth Kochar */ 481bd61d0aSYatharth Kochar ldcopr r0, SCTLR 491bd61d0aSYatharth Kochar orr r0, r0, #SCTLR_I_BIT 501bd61d0aSYatharth Kochar stcopr r0, SCTLR 511bd61d0aSYatharth Kochar isb 521bd61d0aSYatharth Kochar 531bd61d0aSYatharth Kochar /* --------------------------------------------- 541bd61d0aSYatharth Kochar * Since BL2U executes after BL1, it is assumed 551bd61d0aSYatharth Kochar * here that BL1 has already has done the 561bd61d0aSYatharth Kochar * necessary register initializations. 571bd61d0aSYatharth Kochar * --------------------------------------------- 581bd61d0aSYatharth Kochar */ 591bd61d0aSYatharth Kochar 601bd61d0aSYatharth Kochar /* --------------------------------------------- 611bd61d0aSYatharth Kochar * Invalidate the RW memory used by the BL2U 621bd61d0aSYatharth Kochar * image. This includes the data and NOBITS 631bd61d0aSYatharth Kochar * sections. This is done to safeguard against 641bd61d0aSYatharth Kochar * possible corruption of this memory by dirty 651bd61d0aSYatharth Kochar * cache lines in a system cache as a result of 661bd61d0aSYatharth Kochar * use by an earlier boot loader stage. 671bd61d0aSYatharth Kochar * --------------------------------------------- 681bd61d0aSYatharth Kochar */ 691bd61d0aSYatharth Kochar ldr r0, =__RW_START__ 701bd61d0aSYatharth Kochar ldr r1, =__RW_END__ 711bd61d0aSYatharth Kochar sub r1, r1, r0 721bd61d0aSYatharth Kochar bl inv_dcache_range 731bd61d0aSYatharth Kochar 741bd61d0aSYatharth Kochar /* --------------------------------------------- 751bd61d0aSYatharth Kochar * Zero out NOBITS sections. There are 2 of them: 761bd61d0aSYatharth Kochar * - the .bss section; 771bd61d0aSYatharth Kochar * - the coherent memory section. 781bd61d0aSYatharth Kochar * --------------------------------------------- 791bd61d0aSYatharth Kochar */ 801bd61d0aSYatharth Kochar ldr r0, =__BSS_START__ 811bd61d0aSYatharth Kochar ldr r1, =__BSS_SIZE__ 821bd61d0aSYatharth Kochar bl zeromem 831bd61d0aSYatharth Kochar 841bd61d0aSYatharth Kochar /* -------------------------------------------- 851bd61d0aSYatharth Kochar * Allocate a stack whose memory will be marked 861bd61d0aSYatharth Kochar * as Normal-IS-WBWA when the MMU is enabled. 871bd61d0aSYatharth Kochar * There is no risk of reading stale stack 881bd61d0aSYatharth Kochar * memory after enabling the MMU as only the 891bd61d0aSYatharth Kochar * primary cpu is running at the moment. 901bd61d0aSYatharth Kochar * -------------------------------------------- 911bd61d0aSYatharth Kochar */ 921bd61d0aSYatharth Kochar bl plat_set_my_stack 931bd61d0aSYatharth Kochar 941bd61d0aSYatharth Kochar /* --------------------------------------------- 951bd61d0aSYatharth Kochar * Initialize the stack protector canary before 961bd61d0aSYatharth Kochar * any C code is called. 971bd61d0aSYatharth Kochar * --------------------------------------------- 981bd61d0aSYatharth Kochar */ 991bd61d0aSYatharth Kochar#if STACK_PROTECTOR_ENABLED 1001bd61d0aSYatharth Kochar bl update_stack_protector_canary 1011bd61d0aSYatharth Kochar#endif 1021bd61d0aSYatharth Kochar 1031bd61d0aSYatharth Kochar /* --------------------------------------------- 1041bd61d0aSYatharth Kochar * Perform early platform setup & platform 1051bd61d0aSYatharth Kochar * specific early arch. setup e.g. mmu setup 1061bd61d0aSYatharth Kochar * --------------------------------------------- 1071bd61d0aSYatharth Kochar */ 1081bd61d0aSYatharth Kochar mov r0, r11 1095c2c88b5SDouglas Raillard mov r1, r10 1101bd61d0aSYatharth Kochar bl bl2u_early_platform_setup 1111bd61d0aSYatharth Kochar bl bl2u_plat_arch_setup 1121bd61d0aSYatharth Kochar 1131bd61d0aSYatharth Kochar /* --------------------------------------------- 1141bd61d0aSYatharth Kochar * Jump to main function. 1151bd61d0aSYatharth Kochar * --------------------------------------------- 1161bd61d0aSYatharth Kochar */ 1171bd61d0aSYatharth Kochar bl bl2u_main 1181bd61d0aSYatharth Kochar 1191bd61d0aSYatharth Kochar /* --------------------------------------------- 1201bd61d0aSYatharth Kochar * Should never reach this point. 1211bd61d0aSYatharth Kochar * --------------------------------------------- 1221bd61d0aSYatharth Kochar */ 1231bd61d0aSYatharth Kochar no_ret plat_panic_handler 1241bd61d0aSYatharth Kochar 1251bd61d0aSYatharth Kocharendfunc bl2u_entrypoint 126