xref: /rk3399_ARM-atf/bl2/bl2_main.c (revision 97043ac98e13a726dbf8b3b41654dca759e3da2c)
14f6ad66aSAchin Gupta /*
2e83b0cadSDan Handley  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
44f6ad66aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta  *
74f6ad66aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta  * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta  *
104f6ad66aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta  * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta  *
144f6ad66aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta  * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta  * prior written permission.
174f6ad66aSAchin Gupta  *
184f6ad66aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta  */
304f6ad66aSAchin Gupta 
31*97043ac9SDan Handley #include <arch.h>
324f6ad66aSAchin Gupta #include <arch_helpers.h>
33*97043ac9SDan Handley #include <assert.h>
344f6ad66aSAchin Gupta #include <bl_common.h>
354f6ad66aSAchin Gupta #include <bl2.h>
3635e98e55SDan Handley #include <debug.h>
37*97043ac9SDan Handley #include <platform.h>
38*97043ac9SDan Handley #include <stdio.h>
395b827a8fSDan Handley #include "bl2_private.h"
404f6ad66aSAchin Gupta 
414f6ad66aSAchin Gupta /*******************************************************************************
424f6ad66aSAchin Gupta  * The only thing to do in BL2 is to load further images and pass control to
434f6ad66aSAchin Gupta  * BL31. The memory occupied by BL2 will be reclaimed by BL3_x stages. BL2 runs
444f6ad66aSAchin Gupta  * entirely in S-EL1. Since arm standard c libraries are not PIC, printf et al
454f6ad66aSAchin Gupta  * are not available. We rely on assertions to signal error conditions
464f6ad66aSAchin Gupta  ******************************************************************************/
474f6ad66aSAchin Gupta void bl2_main(void)
484f6ad66aSAchin Gupta {
49fb037bfbSDan Handley 	meminfo_t *bl2_tzram_layout;
50fb037bfbSDan Handley 	bl31_args_t *bl2_to_bl31_args;
51a3050ed5SAchin Gupta 	unsigned long bl31_base, bl32_base = 0, bl33_base, el_status;
524f6ad66aSAchin Gupta 	unsigned int bl2_load, bl31_load, mode;
534f6ad66aSAchin Gupta 
544f6ad66aSAchin Gupta 	/* Perform remaining generic architectural setup in S-El1 */
554f6ad66aSAchin Gupta 	bl2_arch_setup();
564f6ad66aSAchin Gupta 
574f6ad66aSAchin Gupta 	/* Perform platform setup in BL1 */
584f6ad66aSAchin Gupta 	bl2_platform_setup();
594f6ad66aSAchin Gupta 
60fb052462SJon Medhurst 	printf("BL2 %s\n\r", build_message);
614f6ad66aSAchin Gupta 
624f6ad66aSAchin Gupta 	/* Find out how much free trusted ram remains after BL2 load */
63ee12f6f7SSandrine Bailleux 	bl2_tzram_layout = bl2_plat_sec_mem_layout();
644f6ad66aSAchin Gupta 
654f6ad66aSAchin Gupta 	/*
664f6ad66aSAchin Gupta 	 * Load BL31. BL1 tells BL2 whether it has been TOP or BOTTOM loaded.
674f6ad66aSAchin Gupta 	 * To avoid fragmentation of trusted SRAM memory, BL31 is always
684f6ad66aSAchin Gupta 	 * loaded opposite to BL2. This allows BL31 to reclaim BL2 memory
694f6ad66aSAchin Gupta 	 * while maintaining its free space in one contiguous chunk.
704f6ad66aSAchin Gupta 	 */
71ee12f6f7SSandrine Bailleux 	bl2_load = bl2_tzram_layout->attr & LOAD_MASK;
724f6ad66aSAchin Gupta 	assert((bl2_load == TOP_LOAD) || (bl2_load == BOT_LOAD));
734f6ad66aSAchin Gupta 	bl31_load = (bl2_load == TOP_LOAD) ? BOT_LOAD : TOP_LOAD;
74ee12f6f7SSandrine Bailleux 	bl31_base = load_image(bl2_tzram_layout, BL31_IMAGE_NAME,
754f6ad66aSAchin Gupta 	                       bl31_load, BL31_BASE);
764f6ad66aSAchin Gupta 
774f6ad66aSAchin Gupta 	/* Assert if it has not been possible to load BL31 */
78e4d084eaSAchin Gupta 	if (bl31_base == 0) {
79e4d084eaSAchin Gupta 		ERROR("Failed to load BL3-1.\n");
80e4d084eaSAchin Gupta 		panic();
81e4d084eaSAchin Gupta 	}
82e4d084eaSAchin Gupta 
83e4d084eaSAchin Gupta 	/*
84e4d084eaSAchin Gupta 	 * Get a pointer to the memory the platform has set aside to pass
85e4d084eaSAchin Gupta 	 * information to BL31.
86e4d084eaSAchin Gupta 	 */
87e4d084eaSAchin Gupta 	bl2_to_bl31_args = bl2_get_bl31_args_ptr();
884f6ad66aSAchin Gupta 
894f6ad66aSAchin Gupta 	/*
90a3050ed5SAchin Gupta 	 * Load the BL32 image if there's one. It is upto to platform
91a3050ed5SAchin Gupta 	 * to specify where BL32 should be loaded if it exists. It
92a3050ed5SAchin Gupta 	 * could create space in the secure sram or point to a
93a3050ed5SAchin Gupta 	 * completely different memory. A zero size indicates that the
94a3050ed5SAchin Gupta 	 * platform does not want to load a BL32 image.
95a3050ed5SAchin Gupta 	 */
96a3050ed5SAchin Gupta 	if (bl2_to_bl31_args->bl32_meminfo.total_size)
97a3050ed5SAchin Gupta 		bl32_base = load_image(&bl2_to_bl31_args->bl32_meminfo,
98a3050ed5SAchin Gupta 				       BL32_IMAGE_NAME,
99a3050ed5SAchin Gupta 				       bl2_to_bl31_args->bl32_meminfo.attr &
100a3050ed5SAchin Gupta 				       LOAD_MASK,
101a3050ed5SAchin Gupta 				       BL32_BASE);
102a3050ed5SAchin Gupta 
103a3050ed5SAchin Gupta 	/*
1044f6ad66aSAchin Gupta 	 * Create a new layout of memory for BL31 as seen by BL2. This
1054f6ad66aSAchin Gupta 	 * will gobble up all the BL2 memory.
1064f6ad66aSAchin Gupta 	 */
107e4d084eaSAchin Gupta 	init_bl31_mem_layout(bl2_tzram_layout,
108e4d084eaSAchin Gupta 			     &bl2_to_bl31_args->bl31_meminfo,
109e4d084eaSAchin Gupta 			     bl31_load);
1104f6ad66aSAchin Gupta 
111e4d084eaSAchin Gupta 	/* Load the BL33 image in non-secure memory provided by the platform */
112e4d084eaSAchin Gupta 	bl33_base = load_image(&bl2_to_bl31_args->bl33_meminfo,
113e4d084eaSAchin Gupta 			       BL33_IMAGE_NAME,
114e4d084eaSAchin Gupta 			       BOT_LOAD,
115e4d084eaSAchin Gupta 			       plat_get_ns_image_entrypoint());
116561cd33eSHarry Liebel 	/* Halt if failed to load normal world firmware. */
117561cd33eSHarry Liebel 	if (bl33_base == 0) {
118561cd33eSHarry Liebel 		ERROR("Failed to load BL3-3.\n");
119561cd33eSHarry Liebel 		panic();
120561cd33eSHarry Liebel 	}
121561cd33eSHarry Liebel 
1224f6ad66aSAchin Gupta 	/*
1234f6ad66aSAchin Gupta 	 * BL2 also needs to tell BL31 where the non-trusted software image
124e4d084eaSAchin Gupta 	 * is located.
1254f6ad66aSAchin Gupta 	 */
126e4d084eaSAchin Gupta 	bl2_to_bl31_args->bl33_image_info.entrypoint = bl33_base;
1274f6ad66aSAchin Gupta 
1284f6ad66aSAchin Gupta 	/* Figure out what mode we enter the non-secure world in */
1294f6ad66aSAchin Gupta 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
1304f6ad66aSAchin Gupta 	el_status &= ID_AA64PFR0_ELX_MASK;
1314f6ad66aSAchin Gupta 
1324f6ad66aSAchin Gupta 	if (el_status)
1334f6ad66aSAchin Gupta 		mode = MODE_EL2;
1344f6ad66aSAchin Gupta 	else
1354f6ad66aSAchin Gupta 		mode = MODE_EL1;
1364f6ad66aSAchin Gupta 
137e4d084eaSAchin Gupta 	/*
138e4d084eaSAchin Gupta 	 * TODO: Consider the possibility of specifying the SPSR in
139e4d084eaSAchin Gupta 	 * the FIP ToC and allowing the platform to have a say as
140e4d084eaSAchin Gupta 	 * well.
141e4d084eaSAchin Gupta 	 */
142e4d084eaSAchin Gupta 	bl2_to_bl31_args->bl33_image_info.spsr =
143e4d084eaSAchin Gupta 		make_spsr(mode, MODE_SP_ELX, MODE_RW_64);
144e4d084eaSAchin Gupta 	bl2_to_bl31_args->bl33_image_info.security_state = NON_SECURE;
145e4d084eaSAchin Gupta 
146a3050ed5SAchin Gupta 	if (bl32_base) {
147a3050ed5SAchin Gupta 		/* Fill BL32 image info */
148a3050ed5SAchin Gupta 		bl2_to_bl31_args->bl32_image_info.entrypoint = bl32_base;
149a3050ed5SAchin Gupta 		bl2_to_bl31_args->bl32_image_info.security_state = SECURE;
150a3050ed5SAchin Gupta 
151a3050ed5SAchin Gupta 		/*
152a3050ed5SAchin Gupta 		 * The Secure Payload Dispatcher service is responsible for
153a3050ed5SAchin Gupta 		 * setting the SPSR prior to entry into the BL32 image.
154a3050ed5SAchin Gupta 		 */
155a3050ed5SAchin Gupta 		bl2_to_bl31_args->bl32_image_info.spsr = 0;
156a3050ed5SAchin Gupta 	}
157a3050ed5SAchin Gupta 
158e4d084eaSAchin Gupta 	/* Flush the entire BL31 args buffer */
159e4d084eaSAchin Gupta 	flush_dcache_range((unsigned long) bl2_to_bl31_args,
160e4d084eaSAchin Gupta 			   sizeof(*bl2_to_bl31_args));
1614f6ad66aSAchin Gupta 
1624f6ad66aSAchin Gupta 	/*
1634f6ad66aSAchin Gupta 	 * Run BL31 via an SMC to BL1. Information on how to pass control to
164e4d084eaSAchin Gupta 	 * the BL32 (if present) and BL33 software images will be passed to
165e4d084eaSAchin Gupta 	 * BL31 as an argument.
1664f6ad66aSAchin Gupta 	 */
1674f6ad66aSAchin Gupta 	run_image(bl31_base,
1684f6ad66aSAchin Gupta 		  make_spsr(MODE_EL3, MODE_SP_ELX, MODE_RW_64),
1694f6ad66aSAchin Gupta 		  SECURE,
170e4d084eaSAchin Gupta 		  (void *) bl2_to_bl31_args,
171e4d084eaSAchin Gupta 		  NULL);
1724f6ad66aSAchin Gupta }
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