xref: /rk3399_ARM-atf/bl2/bl2_main.c (revision 4112bfa0c223eda73af1cfe57ca7dc926f767dd8)
14f6ad66aSAchin Gupta /*
2e83b0cadSDan Handley  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
44f6ad66aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta  *
74f6ad66aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta  * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta  *
104f6ad66aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta  * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta  *
144f6ad66aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta  * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta  * prior written permission.
174f6ad66aSAchin Gupta  *
184f6ad66aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta  */
304f6ad66aSAchin Gupta 
3197043ac9SDan Handley #include <arch.h>
324f6ad66aSAchin Gupta #include <arch_helpers.h>
3397043ac9SDan Handley #include <assert.h>
344f6ad66aSAchin Gupta #include <bl_common.h>
354f6ad66aSAchin Gupta #include <bl2.h>
3635e98e55SDan Handley #include <debug.h>
3797043ac9SDan Handley #include <platform.h>
3897043ac9SDan Handley #include <stdio.h>
395b827a8fSDan Handley #include "bl2_private.h"
404f6ad66aSAchin Gupta 
414f6ad66aSAchin Gupta /*******************************************************************************
4229fb905dSVikram Kanigiri  * Runs BL31 from the given entry point. It jumps to a higher exception level
4329fb905dSVikram Kanigiri  * through an SMC.
4429fb905dSVikram Kanigiri  ******************************************************************************/
45*4112bfa0SVikram Kanigiri static void __dead2 bl2_run_bl31(entry_point_info_t *bl31_ep_info,
4629fb905dSVikram Kanigiri 				unsigned long arg1,
4729fb905dSVikram Kanigiri 				unsigned long arg2)
4829fb905dSVikram Kanigiri {
49*4112bfa0SVikram Kanigiri 	/* Set the args pointer */
50*4112bfa0SVikram Kanigiri 	bl31_ep_info->args.arg0 = arg1;
51*4112bfa0SVikram Kanigiri 	bl31_ep_info->args.arg1 = arg2;
5229fb905dSVikram Kanigiri 
53*4112bfa0SVikram Kanigiri 	/* Flush the params to be passed to memory */
54*4112bfa0SVikram Kanigiri 	bl2_plat_flush_bl31_params();
5529fb905dSVikram Kanigiri 
56*4112bfa0SVikram Kanigiri 	smc(RUN_IMAGE, (unsigned long)bl31_ep_info, 0, 0, 0, 0, 0, 0);
5729fb905dSVikram Kanigiri }
5829fb905dSVikram Kanigiri 
5929fb905dSVikram Kanigiri 
6029fb905dSVikram Kanigiri /*******************************************************************************
614f6ad66aSAchin Gupta  * The only thing to do in BL2 is to load further images and pass control to
624f6ad66aSAchin Gupta  * BL31. The memory occupied by BL2 will be reclaimed by BL3_x stages. BL2 runs
634f6ad66aSAchin Gupta  * entirely in S-EL1. Since arm standard c libraries are not PIC, printf et al
644f6ad66aSAchin Gupta  * are not available. We rely on assertions to signal error conditions
654f6ad66aSAchin Gupta  ******************************************************************************/
664f6ad66aSAchin Gupta void bl2_main(void)
674f6ad66aSAchin Gupta {
68fb037bfbSDan Handley 	meminfo_t *bl2_tzram_layout;
69*4112bfa0SVikram Kanigiri 	bl31_params_t *bl2_to_bl31_params;
70*4112bfa0SVikram Kanigiri 	bl31_plat_params_t *bl2_to_bl31_plat_params;
71*4112bfa0SVikram Kanigiri 	unsigned int bl2_load, bl31_load;
72*4112bfa0SVikram Kanigiri 	entry_point_info_t *bl31_ep_info;
73*4112bfa0SVikram Kanigiri 	int e;
744f6ad66aSAchin Gupta 
754f6ad66aSAchin Gupta 	/* Perform remaining generic architectural setup in S-El1 */
764f6ad66aSAchin Gupta 	bl2_arch_setup();
774f6ad66aSAchin Gupta 
784f6ad66aSAchin Gupta 	/* Perform platform setup in BL1 */
794f6ad66aSAchin Gupta 	bl2_platform_setup();
804f6ad66aSAchin Gupta 
81fb052462SJon Medhurst 	printf("BL2 %s\n\r", build_message);
824f6ad66aSAchin Gupta 
834f6ad66aSAchin Gupta 	/* Find out how much free trusted ram remains after BL2 load */
84ee12f6f7SSandrine Bailleux 	bl2_tzram_layout = bl2_plat_sec_mem_layout();
854f6ad66aSAchin Gupta 
864f6ad66aSAchin Gupta 	/*
87*4112bfa0SVikram Kanigiri 	 * Get a pointer to the memory the platform has set aside to pass
88*4112bfa0SVikram Kanigiri 	 * information to BL31.
89*4112bfa0SVikram Kanigiri 	 */
90*4112bfa0SVikram Kanigiri 	bl2_to_bl31_params = bl2_plat_get_bl31_params();
91*4112bfa0SVikram Kanigiri 	bl2_to_bl31_plat_params = bl2_plat_get_bl31_plat_params();
92*4112bfa0SVikram Kanigiri 	bl31_ep_info = bl2_plat_get_bl31_ep_info();
93*4112bfa0SVikram Kanigiri 
94*4112bfa0SVikram Kanigiri 	/*
954f6ad66aSAchin Gupta 	 * Load BL31. BL1 tells BL2 whether it has been TOP or BOTTOM loaded.
964f6ad66aSAchin Gupta 	 * To avoid fragmentation of trusted SRAM memory, BL31 is always
974f6ad66aSAchin Gupta 	 * loaded opposite to BL2. This allows BL31 to reclaim BL2 memory
984f6ad66aSAchin Gupta 	 * while maintaining its free space in one contiguous chunk.
994f6ad66aSAchin Gupta 	 */
100ee12f6f7SSandrine Bailleux 	bl2_load = bl2_tzram_layout->attr & LOAD_MASK;
1014f6ad66aSAchin Gupta 	assert((bl2_load == TOP_LOAD) || (bl2_load == BOT_LOAD));
1024f6ad66aSAchin Gupta 	bl31_load = (bl2_load == TOP_LOAD) ? BOT_LOAD : TOP_LOAD;
103*4112bfa0SVikram Kanigiri 	e = load_image(bl2_tzram_layout,
104*4112bfa0SVikram Kanigiri 			BL31_IMAGE_NAME,
105*4112bfa0SVikram Kanigiri 			bl31_load,
106*4112bfa0SVikram Kanigiri 			BL31_BASE,
107*4112bfa0SVikram Kanigiri 			bl2_to_bl31_params->bl31_image_info,
108*4112bfa0SVikram Kanigiri 			bl31_ep_info);
1094f6ad66aSAchin Gupta 
1104f6ad66aSAchin Gupta 	/* Assert if it has not been possible to load BL31 */
111*4112bfa0SVikram Kanigiri 	if (e) {
112e4d084eaSAchin Gupta 		ERROR("Failed to load BL3-1.\n");
113e4d084eaSAchin Gupta 		panic();
114e4d084eaSAchin Gupta 	}
115e4d084eaSAchin Gupta 
116*4112bfa0SVikram Kanigiri 	bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info,
117*4112bfa0SVikram Kanigiri 				bl31_ep_info);
118a3050ed5SAchin Gupta 
119a3050ed5SAchin Gupta 	/*
1204f6ad66aSAchin Gupta 	 * Create a new layout of memory for BL31 as seen by BL2. This
1214f6ad66aSAchin Gupta 	 * will gobble up all the BL2 memory.
1224f6ad66aSAchin Gupta 	 */
123e4d084eaSAchin Gupta 	init_bl31_mem_layout(bl2_tzram_layout,
124*4112bfa0SVikram Kanigiri 			     &bl2_to_bl31_plat_params->bl31_meminfo,
125e4d084eaSAchin Gupta 			     bl31_load);
1264f6ad66aSAchin Gupta 
127e4d084eaSAchin Gupta 	/* Load the BL33 image in non-secure memory provided by the platform */
128*4112bfa0SVikram Kanigiri 	e = load_image(&bl2_to_bl31_plat_params->bl33_meminfo,
129e4d084eaSAchin Gupta 			BL33_IMAGE_NAME,
130e4d084eaSAchin Gupta 			BOT_LOAD,
131*4112bfa0SVikram Kanigiri 			plat_get_ns_image_entrypoint(),
132*4112bfa0SVikram Kanigiri 			bl2_to_bl31_params->bl33_image_info,
133*4112bfa0SVikram Kanigiri 			bl2_to_bl31_params->bl33_ep_info);
134*4112bfa0SVikram Kanigiri 
135561cd33eSHarry Liebel 	/* Halt if failed to load normal world firmware. */
136*4112bfa0SVikram Kanigiri 	if (e) {
137561cd33eSHarry Liebel 		ERROR("Failed to load BL3-3.\n");
138561cd33eSHarry Liebel 		panic();
139561cd33eSHarry Liebel 	}
140*4112bfa0SVikram Kanigiri 	bl2_plat_set_bl33_ep_info(bl2_to_bl31_params->bl33_image_info,
141*4112bfa0SVikram Kanigiri 				bl2_to_bl31_params->bl33_ep_info);
142e4d084eaSAchin Gupta 
14329fb905dSVikram Kanigiri 	/*
14429fb905dSVikram Kanigiri 	 * Load the BL32 image if there's one. It is upto to platform
14529fb905dSVikram Kanigiri 	 * to specify where BL32 should be loaded if it exists. It
14629fb905dSVikram Kanigiri 	 * could create space in the secure sram or point to a
14729fb905dSVikram Kanigiri 	 * completely different memory. A zero size indicates that the
14829fb905dSVikram Kanigiri 	 * platform does not want to load a BL32 image.
14929fb905dSVikram Kanigiri 	 */
150*4112bfa0SVikram Kanigiri 	if (bl2_to_bl31_plat_params->bl32_meminfo.total_size) {
151*4112bfa0SVikram Kanigiri 		e = load_image(&bl2_to_bl31_plat_params->bl32_meminfo,
15229fb905dSVikram Kanigiri 			       BL32_IMAGE_NAME,
153*4112bfa0SVikram Kanigiri 			       bl2_to_bl31_plat_params->bl32_meminfo.attr &
15429fb905dSVikram Kanigiri 			       LOAD_MASK,
155*4112bfa0SVikram Kanigiri 			       BL32_BASE,
156*4112bfa0SVikram Kanigiri 			       bl2_to_bl31_params->bl32_image_info,
157*4112bfa0SVikram Kanigiri 			       bl2_to_bl31_params->bl32_ep_info);
15829fb905dSVikram Kanigiri 
159*4112bfa0SVikram Kanigiri 		/* Halt if failed to load normal world firmware. */
160*4112bfa0SVikram Kanigiri 		if (e) {
161*4112bfa0SVikram Kanigiri 			WARN("Failed to load BL3-2.\n");
162*4112bfa0SVikram Kanigiri 		} else {
163*4112bfa0SVikram Kanigiri 			bl2_plat_set_bl32_ep_info(
164*4112bfa0SVikram Kanigiri 				bl2_to_bl31_params->bl32_image_info,
165*4112bfa0SVikram Kanigiri 				bl2_to_bl31_params->bl32_ep_info);
166a3050ed5SAchin Gupta 		}
167*4112bfa0SVikram Kanigiri 	}
168*4112bfa0SVikram Kanigiri 
169a3050ed5SAchin Gupta 
1704f6ad66aSAchin Gupta 	/*
1714f6ad66aSAchin Gupta 	 * Run BL31 via an SMC to BL1. Information on how to pass control to
172e4d084eaSAchin Gupta 	 * the BL32 (if present) and BL33 software images will be passed to
173e4d084eaSAchin Gupta 	 * BL31 as an argument.
1744f6ad66aSAchin Gupta 	 */
175*4112bfa0SVikram Kanigiri 	 bl2_run_bl31(bl31_ep_info, (unsigned long)bl2_to_bl31_params,
176*4112bfa0SVikram Kanigiri 				(unsigned long)bl2_to_bl31_plat_params);
1774f6ad66aSAchin Gupta }
178