1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <common/bl_common.ld.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 13OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 14ENTRY(bl2_entrypoint) 15 16MEMORY { 17#if BL2_IN_XIP_MEM 18 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 19 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 20#else 21 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 22#endif 23} 24 25#if !BL2_IN_XIP_MEM 26#define ROM RAM 27#endif 28 29SECTIONS 30{ 31#if BL2_IN_XIP_MEM 32 . = BL2_RO_BASE; 33 ASSERT(. == ALIGN(PAGE_SIZE), 34 "BL2_RO_BASE address is not aligned on a page boundary.") 35#else 36 . = BL2_BASE; 37 ASSERT(. == ALIGN(PAGE_SIZE), 38 "BL2_BASE address is not aligned on a page boundary.") 39#endif 40 41#if SEPARATE_CODE_AND_RODATA 42 .text . : { 43 __TEXT_START__ = .; 44 __TEXT_RESIDENT_START__ = .; 45 *bl2_el3_entrypoint.o(.text*) 46 *(.text.asm.*) 47 __TEXT_RESIDENT_END__ = .; 48 *(SORT_BY_ALIGNMENT(.text*)) 49 *(.vectors) 50 . = ALIGN(PAGE_SIZE); 51 __TEXT_END__ = .; 52 } >ROM 53 54 .rodata . : { 55 __RODATA_START__ = .; 56 *(SORT_BY_ALIGNMENT(.rodata*)) 57 58 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 59 . = ALIGN(8); 60 __PARSER_LIB_DESCS_START__ = .; 61 KEEP(*(.img_parser_lib_descs)) 62 __PARSER_LIB_DESCS_END__ = .; 63 64 /* 65 * Ensure 8-byte alignment for cpu_ops so that its fields are also 66 * aligned. Also ensure cpu_ops inclusion. 67 */ 68 . = ALIGN(8); 69 __CPU_OPS_START__ = .; 70 KEEP(*(cpu_ops)) 71 __CPU_OPS_END__ = .; 72 73 /* 74 * Keep the .got section in the RO section as it is patched 75 * prior to enabling the MMU and having the .got in RO is better for 76 * security. GOT is a table of addresses so ensure 8-byte alignment. 77 */ 78 . = ALIGN(8); 79 __GOT_START__ = .; 80 *(.got) 81 __GOT_END__ = .; 82 83 . = ALIGN(PAGE_SIZE); 84 __RODATA_END__ = .; 85 } >ROM 86 87 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, 88 "Resident part of BL2 has exceeded its limit.") 89#else 90 ro . : { 91 __RO_START__ = .; 92 __TEXT_RESIDENT_START__ = .; 93 *bl2_el3_entrypoint.o(.text*) 94 *(.text.asm.*) 95 __TEXT_RESIDENT_END__ = .; 96 *(SORT_BY_ALIGNMENT(.text*)) 97 *(SORT_BY_ALIGNMENT(.rodata*)) 98 99 /* 100 * Ensure 8-byte alignment for cpu_ops so that its fields are also 101 * aligned. Also ensure cpu_ops inclusion. 102 */ 103 . = ALIGN(8); 104 __CPU_OPS_START__ = .; 105 KEEP(*(cpu_ops)) 106 __CPU_OPS_END__ = .; 107 108 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 109 . = ALIGN(8); 110 __PARSER_LIB_DESCS_START__ = .; 111 KEEP(*(.img_parser_lib_descs)) 112 __PARSER_LIB_DESCS_END__ = .; 113 114 /* 115 * Keep the .got section in the RO section as it is patched 116 * prior to enabling the MMU and having the .got in RO is better for 117 * security. GOT is a table of addresses so ensure 8-byte alignment. 118 */ 119 . = ALIGN(8); 120 __GOT_START__ = .; 121 *(.got) 122 __GOT_END__ = .; 123 124 *(.vectors) 125 __RO_END_UNALIGNED__ = .; 126 /* 127 * Memory page(s) mapped to this section will be marked as 128 * read-only, executable. No RW data from the next section must 129 * creep in. Ensure the rest of the current memory page is unused. 130 */ 131 . = ALIGN(PAGE_SIZE); 132 133 __RO_END__ = .; 134 } >ROM 135#endif 136 137 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 138 "cpu_ops not defined for this platform.") 139 140#if BL2_IN_XIP_MEM 141 . = BL2_RW_BASE; 142 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 143 "BL2_RW_BASE address is not aligned on a page boundary.") 144#endif 145 146 /* 147 * Define a linker symbol to mark start of the RW memory area for this 148 * image. 149 */ 150 __RW_START__ = . ; 151 152 /* 153 * .data must be placed at a lower address than the stacks if the stack 154 * protector is enabled. Alternatively, the .data.stack_protector_canary 155 * section can be placed independently of the main .data section. 156 */ 157 .data . : { 158 __DATA_RAM_START__ = .; 159 *(SORT_BY_ALIGNMENT(.data*)) 160 __DATA_RAM_END__ = .; 161 } >RAM AT>ROM 162 163 /* 164 * .rela.dyn needs to come after .data for the read-elf utility to parse 165 * this section correctly. Ensure 8-byte alignment so that the fields of 166 * RELA data structure are aligned. 167 */ 168 . = ALIGN(8); 169 __RELA_START__ = .; 170 .rela.dyn . : { 171 } >RAM 172 __RELA_END__ = .; 173 174 stacks (NOLOAD) : { 175 __STACKS_START__ = .; 176 *(tzfw_normal_stacks) 177 __STACKS_END__ = .; 178 } >RAM 179 180 /* 181 * The .bss section gets initialised to 0 at runtime. 182 * Its base address should be 16-byte aligned for better performance of the 183 * zero-initialization code. 184 */ 185 .bss : ALIGN(16) { 186 __BSS_START__ = .; 187 *(SORT_BY_ALIGNMENT(.bss*)) 188 *(COMMON) 189 __BSS_END__ = .; 190 } >RAM 191 192 XLAT_TABLE_SECTION >RAM 193 194#if USE_COHERENT_MEM 195 /* 196 * The base address of the coherent memory section must be page-aligned (4K) 197 * to guarantee that the coherent data are stored on their own pages and 198 * are not mixed with normal data. This is required to set up the correct 199 * memory attributes for the coherent data page tables. 200 */ 201 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 202 __COHERENT_RAM_START__ = .; 203 *(tzfw_coherent_mem) 204 __COHERENT_RAM_END_UNALIGNED__ = .; 205 /* 206 * Memory page(s) mapped to this section will be marked 207 * as device memory. No other unexpected data must creep in. 208 * Ensure the rest of the current memory page is unused. 209 */ 210 . = ALIGN(PAGE_SIZE); 211 __COHERENT_RAM_END__ = .; 212 } >RAM 213#endif 214 215 /* 216 * Define a linker symbol to mark end of the RW memory area for this 217 * image. 218 */ 219 __RW_END__ = .; 220 __BL2_END__ = .; 221 222 /DISCARD/ : { 223 *(.dynsym .dynstr .hash .gnu.hash) 224 } 225 226#if BL2_IN_XIP_MEM 227 __BL2_RAM_START__ = ADDR(.data); 228 __BL2_RAM_END__ = .; 229 230 __DATA_ROM_START__ = LOADADDR(.data); 231 __DATA_SIZE__ = SIZEOF(.data); 232 233 /* 234 * The .data section is the last PROGBITS section so its end marks the end 235 * of BL2's RO content in XIP memory.. 236 */ 237 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 238 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 239 "BL2's RO content has exceeded its limit.") 240#endif 241 __BSS_SIZE__ = SIZEOF(.bss); 242 243 244#if USE_COHERENT_MEM 245 __COHERENT_RAM_UNALIGNED_SIZE__ = 246 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 247#endif 248 249#if BL2_IN_XIP_MEM 250 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 251#else 252 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 253#endif 254} 255