1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15#if BL2_IN_XIP_MEM 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 18#else 19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 20#endif 21} 22 23#if !BL2_IN_XIP_MEM 24#define ROM RAM 25#endif 26 27SECTIONS 28{ 29#if BL2_IN_XIP_MEM 30 . = BL2_RO_BASE; 31 ASSERT(. == ALIGN(PAGE_SIZE), 32 "BL2_RO_BASE address is not aligned on a page boundary.") 33#else 34 . = BL2_BASE; 35 ASSERT(. == ALIGN(PAGE_SIZE), 36 "BL2_BASE address is not aligned on a page boundary.") 37#endif 38 39#if SEPARATE_CODE_AND_RODATA 40 .text . : { 41 __TEXT_START__ = .; 42 __TEXT_RESIDENT_START__ = .; 43 *bl2_el3_entrypoint.o(.text*) 44 *(.text.asm.*) 45 __TEXT_RESIDENT_END__ = .; 46 *(SORT_BY_ALIGNMENT(.text*)) 47 *(.vectors) 48 . = ALIGN(PAGE_SIZE); 49 __TEXT_END__ = .; 50 } >ROM 51 52 .rodata . : { 53 __RODATA_START__ = .; 54 *(SORT_BY_ALIGNMENT(.rodata*)) 55 56 RODATA_COMMON 57 58 . = ALIGN(PAGE_SIZE); 59 __RODATA_END__ = .; 60 } >ROM 61 62 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, 63 "Resident part of BL2 has exceeded its limit.") 64#else 65 ro . : { 66 __RO_START__ = .; 67 __TEXT_RESIDENT_START__ = .; 68 *bl2_el3_entrypoint.o(.text*) 69 *(.text.asm.*) 70 __TEXT_RESIDENT_END__ = .; 71 *(SORT_BY_ALIGNMENT(.text*)) 72 *(SORT_BY_ALIGNMENT(.rodata*)) 73 74 RODATA_COMMON 75 76 *(.vectors) 77 __RO_END_UNALIGNED__ = .; 78 /* 79 * Memory page(s) mapped to this section will be marked as 80 * read-only, executable. No RW data from the next section must 81 * creep in. Ensure the rest of the current memory page is unused. 82 */ 83 . = ALIGN(PAGE_SIZE); 84 85 __RO_END__ = .; 86 } >ROM 87#endif 88 89 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 90 "cpu_ops not defined for this platform.") 91 92#if BL2_IN_XIP_MEM 93 . = BL2_RW_BASE; 94 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 95 "BL2_RW_BASE address is not aligned on a page boundary.") 96#endif 97 98 /* 99 * Define a linker symbol to mark start of the RW memory area for this 100 * image. 101 */ 102 __RW_START__ = . ; 103 104 /* 105 * .data must be placed at a lower address than the stacks if the stack 106 * protector is enabled. Alternatively, the .data.stack_protector_canary 107 * section can be placed independently of the main .data section. 108 */ 109 .data . : { 110 __DATA_RAM_START__ = .; 111 *(SORT_BY_ALIGNMENT(.data*)) 112 __DATA_RAM_END__ = .; 113 } >RAM AT>ROM 114 115 /* 116 * .rela.dyn needs to come after .data for the read-elf utility to parse 117 * this section correctly. Ensure 8-byte alignment so that the fields of 118 * RELA data structure are aligned. 119 */ 120 . = ALIGN(8); 121 __RELA_START__ = .; 122 .rela.dyn . : { 123 } >RAM 124 __RELA_END__ = .; 125 126 stacks (NOLOAD) : { 127 __STACKS_START__ = .; 128 *(tzfw_normal_stacks) 129 __STACKS_END__ = .; 130 } >RAM 131 132 BSS_SECTION >RAM 133 XLAT_TABLE_SECTION >RAM 134 135#if USE_COHERENT_MEM 136 /* 137 * The base address of the coherent memory section must be page-aligned (4K) 138 * to guarantee that the coherent data are stored on their own pages and 139 * are not mixed with normal data. This is required to set up the correct 140 * memory attributes for the coherent data page tables. 141 */ 142 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 143 __COHERENT_RAM_START__ = .; 144 *(tzfw_coherent_mem) 145 __COHERENT_RAM_END_UNALIGNED__ = .; 146 /* 147 * Memory page(s) mapped to this section will be marked 148 * as device memory. No other unexpected data must creep in. 149 * Ensure the rest of the current memory page is unused. 150 */ 151 . = ALIGN(PAGE_SIZE); 152 __COHERENT_RAM_END__ = .; 153 } >RAM 154#endif 155 156 /* 157 * Define a linker symbol to mark end of the RW memory area for this 158 * image. 159 */ 160 __RW_END__ = .; 161 __BL2_END__ = .; 162 163 /DISCARD/ : { 164 *(.dynsym .dynstr .hash .gnu.hash) 165 } 166 167#if BL2_IN_XIP_MEM 168 __BL2_RAM_START__ = ADDR(.data); 169 __BL2_RAM_END__ = .; 170 171 __DATA_ROM_START__ = LOADADDR(.data); 172 __DATA_SIZE__ = SIZEOF(.data); 173 174 /* 175 * The .data section is the last PROGBITS section so its end marks the end 176 * of BL2's RO content in XIP memory.. 177 */ 178 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 179 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 180 "BL2's RO content has exceeded its limit.") 181#endif 182 __BSS_SIZE__ = SIZEOF(.bss); 183 184 185#if USE_COHERENT_MEM 186 __COHERENT_RAM_UNALIGNED_SIZE__ = 187 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 188#endif 189 190#if BL2_IN_XIP_MEM 191 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 192#else 193 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 194#endif 195} 196