xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision c948f77136c42a92d0bb660543a3600c36dcf7f1) 
1/*
2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <lib/xlat_tables/xlat_tables_defs.h>
10
11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
12OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
13ENTRY(bl2_entrypoint)
14
15MEMORY {
16    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
17}
18
19
20SECTIONS
21{
22    . = BL2_BASE;
23    ASSERT(. == ALIGN(PAGE_SIZE),
24           "BL2_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29        *bl2_entrypoint.o(.text*)
30        *(.text*)
31        *(.vectors)
32        . = ALIGN(PAGE_SIZE);
33        __TEXT_END__ = .;
34     } >RAM
35
36     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
37     .ARM.extab . : {
38        *(.ARM.extab* .gnu.linkonce.armextab.*)
39     } >RAM
40
41     .ARM.exidx . : {
42        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
43     } >RAM
44
45    .rodata . : {
46        __RODATA_START__ = .;
47        *(.rodata*)
48
49        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
50        . = ALIGN(8);
51        __PARSER_LIB_DESCS_START__ = .;
52        KEEP(*(.img_parser_lib_descs))
53        __PARSER_LIB_DESCS_END__ = .;
54
55        . = ALIGN(PAGE_SIZE);
56        __RODATA_END__ = .;
57    } >RAM
58#else
59    ro . : {
60        __RO_START__ = .;
61        *bl2_entrypoint.o(.text*)
62        *(.text*)
63        *(.rodata*)
64
65        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
66        . = ALIGN(8);
67        __PARSER_LIB_DESCS_START__ = .;
68        KEEP(*(.img_parser_lib_descs))
69        __PARSER_LIB_DESCS_END__ = .;
70
71        *(.vectors)
72        __RO_END_UNALIGNED__ = .;
73        /*
74         * Memory page(s) mapped to this section will be marked as
75         * read-only, executable.  No RW data from the next section must
76         * creep in.  Ensure the rest of the current memory page is unused.
77         */
78        . = ALIGN(PAGE_SIZE);
79        __RO_END__ = .;
80    } >RAM
81#endif
82
83    /*
84     * Define a linker symbol to mark start of the RW memory area for this
85     * image.
86     */
87    __RW_START__ = . ;
88
89    /*
90     * .data must be placed at a lower address than the stacks if the stack
91     * protector is enabled. Alternatively, the .data.stack_protector_canary
92     * section can be placed independently of the main .data section.
93     */
94    .data . : {
95        __DATA_START__ = .;
96        *(.data*)
97        __DATA_END__ = .;
98    } >RAM
99
100    stacks (NOLOAD) : {
101        __STACKS_START__ = .;
102        *(tzfw_normal_stacks)
103        __STACKS_END__ = .;
104    } >RAM
105
106    /*
107     * The .bss section gets initialised to 0 at runtime.
108     * Its base address should be 16-byte aligned for better performance of the
109     * zero-initialization code.
110     */
111    .bss : ALIGN(16) {
112        __BSS_START__ = .;
113        *(SORT_BY_ALIGNMENT(.bss*))
114        *(COMMON)
115        __BSS_END__ = .;
116    } >RAM
117
118    /*
119     * The xlat_table section is for full, aligned page tables (4K).
120     * Removing them from .bss avoids forcing 4K alignment on
121     * the .bss section. The tables are initialized to zero by the translation
122     * tables library.
123     */
124    xlat_table (NOLOAD) : {
125        *(xlat_table)
126    } >RAM
127
128#if USE_COHERENT_MEM
129    /*
130     * The base address of the coherent memory section must be page-aligned (4K)
131     * to guarantee that the coherent data are stored on their own pages and
132     * are not mixed with normal data.  This is required to set up the correct
133     * memory attributes for the coherent data page tables.
134     */
135    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
136        __COHERENT_RAM_START__ = .;
137        *(tzfw_coherent_mem)
138        __COHERENT_RAM_END_UNALIGNED__ = .;
139        /*
140         * Memory page(s) mapped to this section will be marked
141         * as device memory.  No other unexpected data must creep in.
142         * Ensure the rest of the current memory page is unused.
143         */
144        . = ALIGN(PAGE_SIZE);
145        __COHERENT_RAM_END__ = .;
146    } >RAM
147#endif
148
149    /*
150     * Define a linker symbol to mark end of the RW memory area for this
151     * image.
152     */
153    __RW_END__ = .;
154    __BL2_END__ = .;
155
156    __BSS_SIZE__ = SIZEOF(.bss);
157
158#if USE_COHERENT_MEM
159    __COHERENT_RAM_UNALIGNED_SIZE__ =
160        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
161#endif
162
163    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
164}
165