1*b1d27b48SRoberto Vargas/* 2*b1d27b48SRoberto Vargas * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*b1d27b48SRoberto Vargas * 4*b1d27b48SRoberto Vargas * SPDX-License-Identifier: BSD-3-Clause 5*b1d27b48SRoberto Vargas */ 6*b1d27b48SRoberto Vargas 7*b1d27b48SRoberto Vargas#include <arch.h> 8*b1d27b48SRoberto Vargas#include <asm_macros.S> 9*b1d27b48SRoberto Vargas#include <bl1.h> 10*b1d27b48SRoberto Vargas#include <bl_common.h> 11*b1d27b48SRoberto Vargas#include <context.h> 12*b1d27b48SRoberto Vargas 13*b1d27b48SRoberto Vargas/* ----------------------------------------------------------------------------- 14*b1d27b48SRoberto Vargas * Very simple stackless exception handlers used by BL2. 15*b1d27b48SRoberto Vargas * ----------------------------------------------------------------------------- 16*b1d27b48SRoberto Vargas */ 17*b1d27b48SRoberto Vargas .globl bl2_el3_exceptions 18*b1d27b48SRoberto Vargas 19*b1d27b48SRoberto Vargasvector_base bl2_el3_exceptions 20*b1d27b48SRoberto Vargas 21*b1d27b48SRoberto Vargas /* ----------------------------------------------------- 22*b1d27b48SRoberto Vargas * Current EL with SP0 : 0x0 - 0x200 23*b1d27b48SRoberto Vargas * ----------------------------------------------------- 24*b1d27b48SRoberto Vargas */ 25*b1d27b48SRoberto Vargasvector_entry SynchronousExceptionSP0 26*b1d27b48SRoberto Vargas mov x0, #SYNC_EXCEPTION_SP_EL0 27*b1d27b48SRoberto Vargas bl plat_report_exception 28*b1d27b48SRoberto Vargas no_ret plat_panic_handler 29*b1d27b48SRoberto Vargas check_vector_size SynchronousExceptionSP0 30*b1d27b48SRoberto Vargas 31*b1d27b48SRoberto Vargasvector_entry IrqSP0 32*b1d27b48SRoberto Vargas mov x0, #IRQ_SP_EL0 33*b1d27b48SRoberto Vargas bl plat_report_exception 34*b1d27b48SRoberto Vargas no_ret plat_panic_handler 35*b1d27b48SRoberto Vargas check_vector_size IrqSP0 36*b1d27b48SRoberto Vargas 37*b1d27b48SRoberto Vargasvector_entry FiqSP0 38*b1d27b48SRoberto Vargas mov x0, #FIQ_SP_EL0 39*b1d27b48SRoberto Vargas bl plat_report_exception 40*b1d27b48SRoberto Vargas no_ret plat_panic_handler 41*b1d27b48SRoberto Vargas check_vector_size FiqSP0 42*b1d27b48SRoberto Vargas 43*b1d27b48SRoberto Vargasvector_entry SErrorSP0 44*b1d27b48SRoberto Vargas mov x0, #SERROR_SP_EL0 45*b1d27b48SRoberto Vargas bl plat_report_exception 46*b1d27b48SRoberto Vargas no_ret plat_panic_handler 47*b1d27b48SRoberto Vargas check_vector_size SErrorSP0 48*b1d27b48SRoberto Vargas 49*b1d27b48SRoberto Vargas /* ----------------------------------------------------- 50*b1d27b48SRoberto Vargas * Current EL with SPx: 0x200 - 0x400 51*b1d27b48SRoberto Vargas * ----------------------------------------------------- 52*b1d27b48SRoberto Vargas */ 53*b1d27b48SRoberto Vargasvector_entry SynchronousExceptionSPx 54*b1d27b48SRoberto Vargas mov x0, #SYNC_EXCEPTION_SP_ELX 55*b1d27b48SRoberto Vargas bl plat_report_exception 56*b1d27b48SRoberto Vargas no_ret plat_panic_handler 57*b1d27b48SRoberto Vargas check_vector_size SynchronousExceptionSPx 58*b1d27b48SRoberto Vargas 59*b1d27b48SRoberto Vargasvector_entry IrqSPx 60*b1d27b48SRoberto Vargas mov x0, #IRQ_SP_ELX 61*b1d27b48SRoberto Vargas bl plat_report_exception 62*b1d27b48SRoberto Vargas no_ret plat_panic_handler 63*b1d27b48SRoberto Vargas check_vector_size IrqSPx 64*b1d27b48SRoberto Vargas 65*b1d27b48SRoberto Vargasvector_entry FiqSPx 66*b1d27b48SRoberto Vargas mov x0, #FIQ_SP_ELX 67*b1d27b48SRoberto Vargas bl plat_report_exception 68*b1d27b48SRoberto Vargas no_ret plat_panic_handler 69*b1d27b48SRoberto Vargas check_vector_size FiqSPx 70*b1d27b48SRoberto Vargas 71*b1d27b48SRoberto Vargasvector_entry SErrorSPx 72*b1d27b48SRoberto Vargas mov x0, #SERROR_SP_ELX 73*b1d27b48SRoberto Vargas bl plat_report_exception 74*b1d27b48SRoberto Vargas no_ret plat_panic_handler 75*b1d27b48SRoberto Vargas check_vector_size SErrorSPx 76*b1d27b48SRoberto Vargas 77*b1d27b48SRoberto Vargas /* ----------------------------------------------------- 78*b1d27b48SRoberto Vargas * Lower EL using AArch64 : 0x400 - 0x600 79*b1d27b48SRoberto Vargas * ----------------------------------------------------- 80*b1d27b48SRoberto Vargas */ 81*b1d27b48SRoberto Vargasvector_entry SynchronousExceptionA64 82*b1d27b48SRoberto Vargas mov x0, #SYNC_EXCEPTION_AARCH64 83*b1d27b48SRoberto Vargas bl plat_report_exception 84*b1d27b48SRoberto Vargas no_ret plat_panic_handler 85*b1d27b48SRoberto Vargas check_vector_size SynchronousExceptionA64 86*b1d27b48SRoberto Vargas 87*b1d27b48SRoberto Vargasvector_entry IrqA64 88*b1d27b48SRoberto Vargas mov x0, #IRQ_AARCH64 89*b1d27b48SRoberto Vargas bl plat_report_exception 90*b1d27b48SRoberto Vargas no_ret plat_panic_handler 91*b1d27b48SRoberto Vargas check_vector_size IrqA64 92*b1d27b48SRoberto Vargas 93*b1d27b48SRoberto Vargasvector_entry FiqA64 94*b1d27b48SRoberto Vargas mov x0, #FIQ_AARCH64 95*b1d27b48SRoberto Vargas bl plat_report_exception 96*b1d27b48SRoberto Vargas no_ret plat_panic_handler 97*b1d27b48SRoberto Vargas check_vector_size FiqA64 98*b1d27b48SRoberto Vargas 99*b1d27b48SRoberto Vargasvector_entry SErrorA64 100*b1d27b48SRoberto Vargas mov x0, #SERROR_AARCH64 101*b1d27b48SRoberto Vargas bl plat_report_exception 102*b1d27b48SRoberto Vargas no_ret plat_panic_handler 103*b1d27b48SRoberto Vargas check_vector_size SErrorA64 104*b1d27b48SRoberto Vargas 105*b1d27b48SRoberto Vargas /* ----------------------------------------------------- 106*b1d27b48SRoberto Vargas * Lower EL using AArch32 : 0x600 - 0x800 107*b1d27b48SRoberto Vargas * ----------------------------------------------------- 108*b1d27b48SRoberto Vargas */ 109*b1d27b48SRoberto Vargasvector_entry SynchronousExceptionA32 110*b1d27b48SRoberto Vargas mov x0, #SYNC_EXCEPTION_AARCH32 111*b1d27b48SRoberto Vargas bl plat_report_exception 112*b1d27b48SRoberto Vargas no_ret plat_panic_handler 113*b1d27b48SRoberto Vargas check_vector_size SynchronousExceptionA32 114*b1d27b48SRoberto Vargas 115*b1d27b48SRoberto Vargasvector_entry IrqA32 116*b1d27b48SRoberto Vargas mov x0, #IRQ_AARCH32 117*b1d27b48SRoberto Vargas bl plat_report_exception 118*b1d27b48SRoberto Vargas no_ret plat_panic_handler 119*b1d27b48SRoberto Vargas check_vector_size IrqA32 120*b1d27b48SRoberto Vargas 121*b1d27b48SRoberto Vargasvector_entry FiqA32 122*b1d27b48SRoberto Vargas mov x0, #FIQ_AARCH32 123*b1d27b48SRoberto Vargas bl plat_report_exception 124*b1d27b48SRoberto Vargas no_ret plat_panic_handler 125*b1d27b48SRoberto Vargas check_vector_size FiqA32 126*b1d27b48SRoberto Vargas 127*b1d27b48SRoberto Vargasvector_entry SErrorA32 128*b1d27b48SRoberto Vargas mov x0, #SERROR_AARCH32 129*b1d27b48SRoberto Vargas bl plat_report_exception 130*b1d27b48SRoberto Vargas no_ret plat_panic_handler 131*b1d27b48SRoberto Vargas check_vector_size SErrorA32 132