1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <el3_common_macros.S> 11 12 .globl bl2_entrypoint 13 .globl bl2_vector_table 14 .globl bl2_el3_run_image 15 .globl bl2_run_next_image 16 17func bl2_entrypoint 18 /* Save arguments x0-x3 from previous Boot loader */ 19 mov x20, x0 20 mov x21, x1 21 mov x22, x2 22 mov x23, x3 23 24 el3_entrypoint_common \ 25 _init_sctlr=1 \ 26 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 27 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 28 _init_memory=1 \ 29 _init_c_runtime=1 \ 30 _exception_vectors=bl2_el3_exceptions 31 32 /* 33 * Restore parameters of boot rom 34 */ 35 mov x0, x20 36 mov x1, x21 37 mov x2, x22 38 mov x3, x23 39 40 bl bl2_el3_early_platform_setup 41 bl bl2_el3_plat_arch_setup 42 43 /* --------------------------------------------- 44 * Jump to main function. 45 * --------------------------------------------- 46 */ 47 bl bl2_main 48 49 /* --------------------------------------------- 50 * Should never reach this point. 51 * --------------------------------------------- 52 */ 53 no_ret plat_panic_handler 54endfunc bl2_entrypoint 55 56func bl2_run_next_image 57 mov x20,x0 58 /* 59 * MMU needs to be disabled because both BL2 and BL31 execute 60 * in EL3, and therefore share the same address space. 61 * BL31 will initialize the address space according to its 62 * own requirement. 63 */ 64 bl disable_mmu_icache_el3 65 tlbi alle3 66 bl bl2_el3_plat_prepare_exit 67 68 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 69 msr elr_el3, x0 70 msr spsr_el3, x1 71 72 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 73 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 74 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 75 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 76 eret 77endfunc bl2_run_next_image 78