1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <el3_common_macros.S> 11 12 .globl bl2_entrypoint 13 .globl bl2_el3_run_image 14 .globl bl2_run_next_image 15 16func bl2_entrypoint 17 /* Save arguments x0-x3 from previous Boot loader */ 18 mov x20, x0 19 mov x21, x1 20 mov x22, x2 21 mov x23, x3 22 23 el3_entrypoint_common \ 24 _init_sctlr=1 \ 25 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 26 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 27 _init_memory=1 \ 28 _init_c_runtime=1 \ 29 _exception_vectors=bl2_el3_exceptions 30 31 /* --------------------------------------------- 32 * Restore parameters of boot rom 33 * --------------------------------------------- 34 */ 35 mov x0, x20 36 mov x1, x21 37 mov x2, x22 38 mov x3, x23 39 40 /* --------------------------------------------- 41 * Perform BL2 setup 42 * --------------------------------------------- 43 */ 44 bl bl2_el3_setup 45 46 /* --------------------------------------------- 47 * Enable pointer authentication 48 * --------------------------------------------- 49 */ 50#if ENABLE_PAUTH 51 mrs x0, sctlr_el3 52 orr x0, x0, #SCTLR_EnIA_BIT 53#if ENABLE_BTI 54 /* --------------------------------------------- 55 * Enable PAC branch type compatibility 56 * --------------------------------------------- 57 */ 58 bic x0, x0, #SCTLR_BT_BIT 59#endif /* ENABLE_BTI */ 60 msr sctlr_el3, x0 61 isb 62#endif /* ENABLE_PAUTH */ 63 64 /* --------------------------------------------- 65 * Jump to main function. 66 * --------------------------------------------- 67 */ 68 bl bl2_main 69 70 /* --------------------------------------------- 71 * Should never reach this point. 72 * --------------------------------------------- 73 */ 74 no_ret plat_panic_handler 75endfunc bl2_entrypoint 76 77func bl2_run_next_image 78 mov x20,x0 79 /* --------------------------------------------- 80 * MMU needs to be disabled because both BL2 and BL31 execute 81 * in EL3, and therefore share the same address space. 82 * BL31 will initialize the address space according to its 83 * own requirement. 84 * --------------------------------------------- 85 */ 86 bl disable_mmu_icache_el3 87 tlbi alle3 88 bl bl2_el3_plat_prepare_exit 89 90 /* --------------------------------------------- 91 * Disable pointer authentication before jumping to BL31 or that will 92 * cause an authentication failure during the early platform init. 93 * --------------------------------------------- 94 */ 95#if ENABLE_PAUTH 96 mrs x0, sctlr_el3 97 bic x0, x0, #SCTLR_EnIA_BIT 98 msr sctlr_el3, x0 99 isb 100#endif /* ENABLE_PAUTH */ 101 102 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 103 msr elr_el3, x0 104 msr spsr_el3, x1 105 106 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 107 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 108 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 109 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 110 eret 111endfunc bl2_run_next_image 112